Memory emulation using resistivity-sensitive memory
View Patent ↗Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another.
1. A SRAM emulating non-volatile memory, comprising:
a static random access memory (SRAM) interface circuitry positioned in a logic plane and operative to electrically communicate with a plurality of signals configured for SRAM data operations, the plurality of signals including an address signal and at least one data signal; and
a non-volatile memory array vertically positioned over the logic plane and in contact with the logic plane, the non-volatile memory array is electrically coupled with the SRAM interface circuitry, the non-volatile memory array including a plurality of memory elements,
each memory element including two terminals and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the two terminals, the data is retained in the absence of power, the data is written by applying a write voltage across the two terminals, the write voltage is less than the read voltage, and
wherein the SRAM interface circuitry is operative to perform data operations on the non-volatile memory array in response to the plurality of signals and the data operations emulate SRAM data operations.
2. The SRAM emulating non-volatile memory of claim 1 , wherein the logic plane is fabricated in a substrate.
3. The SRAM emulating non-volatile memory of claim 1 , wherein the non-volatile memory array comprises a two-terminal cross-point memory array.
4. The SRAM emulating non-volatile memory of claim 1 , wherein the plurality of signals further comprises
a chip-select signal operative to select the non-volatile memory array for a data operation,
a read-write signal operative to configure the non-volatile memory array for a read operation or a write operation, and
an output enable signal operative output data from the non-volatile memory array during the read operation.
5. The SRAM emulating non-volatile memory of claim 1 , wherein the at least one data signal comprises a selected one of a split data interface where write data is received on a first signal and read data is transmitted on a second signal or a shared data interface where read data and write data are communicated using a single signal.
6. The SRAM emulating non-volatile memory of claim 1 , wherein the SRAM interface circuitry is operative to perform the data operations in a cycle that is approximately no longer in duration than a SRAM data operations cycle.
7. The SRAM emulating non-volatile memory of claim 1 and further comprising:
a plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is vertically stacked upon another of the plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is in contact with the logic plane, and the plurality of the non-volatile memory arrays are electrically coupled with the SRAM interface circuitry.
8. A DRAM emulating non-volatile memory, comprising:
a dynamic random access memory (DRAM) interface circuitry positioned in a logic plane and operative to electrically communicate with a plurality of signals configured for DRAM data operations,
the plurality of signals including an address signal, a RAS signal, a CAS signal, and at least one data signal, the address signal including a row address select (RAS) address and a column address select (CAS) address, the RAS signal operative to indicate transmission of the RAS address and the CAS signal operative to indicate transmission of the CAS; and
a non-volatile memory array vertically positioned over the logic plane and in contact with the logic plane, the non-volatile memory array is electrically coupled with the DRAM interface circuitry, the non-volatile memory array including a plurality of memory elements,
each memory element including two terminals and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the two terminals, the data is retained in the absence of power, the data is written by applying a write voltage across the two terminals, the write voltage is less than the read voltage, and
wherein the DRAM interface circuitry is operative to perform data operations on the non-volatile memory array in response to the plurality of signals and the data operations emulate DRAM data operations.
9. The DRAM emulating non-volatile memory of claim 8 , wherein the logic plane is fabricated in a substrate.
10. The DRAM emulating non-volatile memory of claim 8 , wherein the non-volatile memory array comprises a two-terminal cross-point memory array.
11. The DRAM emulating non-volatile memory of claim 8 , wherein the plurality of signals further comprises
a chip-select signal operative to select the non-volatile memory array for a data operation,
a read-write signal operative to configure the non-volatile memory array for a read operation or a write operation,
an output enable signal operative to enable stored data to be output from the non-volatile memory array during the read operation,
a data clock signal configured to activate when the at least one data signal is transmitting data, and
a clock signal operative to emulate DRAM clock timing.
12. The DRAM emulating non-volatile memory of claim 8 , wherein the at least one data signal comprises a selected one of a split data interface where write data is received on a first signal and read data is transmitted on a second signal or a shared data interface where read data and write data are communicated using a single signal.
13. The DRAM emulating non-volatile memory of claim 8 , wherein the DRAM interface circuitry is operative to perform the data operations in a cycle that is approximately no longer in duration than a DRAM data operations cycle.
14. The DRAM emulating non-volatile memory of claim 8 and further comprising:
a plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is vertically stacked upon one other of the plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is in contact with the logic plane, and the plurality of the non-volatile memory arrays are electrically coupled with the DRAM interface circuitry.