Non-volatile memory with a single transistor and resistive memory element
View Patent ↗Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.
1. A non-volatile RAM memory array comprising:
a plurality of memory cells formed on a semiconductor substrate, each cell capable of being selected through a select line and a data line, whereby the select line and the data line are perpendicular to each other, and having
a transistor that controls current flow through the memory cell depending on the voltage of the select line;
a multi-resistive state material that
changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material;
changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse; and
maintains the resistive state even if power ceases to be supplied to the memory cell;
wherein the resistive state of the memory cell determines the information stored in the memory cell; and
wherein the first voltage pulse and the second voltage pulse have magnitudes between 1 and 10 volts and ate generated from a voltage supply (V CC ) that has been converted to by at least two on-chip voltage converters.
2. A non-volatile RAM memory array comprising:
a plurality of memory cells formed on a semiconductor substrate, each cell capable of being selected through a select line and a data line, whereby the select line and the data line are perpendicular to each other, and having
a transistor that controls current flow through the memory cell depending on the voltage of the select line;
a multi-resistive state material that
changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material;
changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse; and
maintains the resistive state even if power ceases to be supplied to the memory cell;
wherein the resistive state of the memory cell determines the information stored in the memory cell; and
wherein the multi-resistive state material has a resistivity of less than 5 Ω-cm.
3. A non-volatile RAM memory array comprising:
a plurality of memory cells formed on a semiconductor substrate each cell capable of being selected through a select line and a data line, and having
a semiconductor device that controls current flow depending on the voltage of the select line;
a multi-resistive state material that
changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material;
changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse; and
maintains the resistive state even if power ceases to be supplied to the memory cell;
wherein
the resistive state of the memory cell determines the information stored in the memory cell; and
the memory cells are repeated in the direction of the select lines and are alternately flipped along the direction of the data lines.
4. The non-volatile RAM memory array of claim 3 , wherein the reference line is parallel to the select line and spans two adjacent cells in data line direction.
5. The non-volatile RAM memory array of claim 3 , wherein the select line is polysilicon material.
6. A non-volatile RAM memory array, comprising:
a plurality of memory cells formed on a semiconductor substrate, each cell capable of being selected through a select line and a data line, and having
a semiconductor device that is formed on the semiconductor substrate and controls current flow depending on the voltage of the select line; and
a multi-resistive state material that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse, wherein the resistive state of the memory cell determines the information stored in the memory cell; and
wherein the information stored in the plurality of memory cells can be maintained in the absence of power and
wherein the first voltage pulse and the second voltage pulse have magnitudes between 1 and 10 volts and are generated from a voltage supply (V CC ) that has been converted to by at least two on-chip voltage converters.
7. A non-volatile RAM memory array, comprising:
a plurality of memory cells formed on a semiconductor substrate, each cell capable of being selected through a select line and a data line, and having
a semiconductor device that is formed on the semiconductor substrate and controls current flow depending on the voltage of the select line; and
a multi-resistive are material that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse, wherein the resistive state of the memory cell determines the information stored in the memory cell; and
wherein the information stored in the plurality of memory cells can be maintained in the absence of power and
wherein the multi-resistive state material has a resistivity of less than 5 Ω-cm.
8. A non-volatile RAM memory array comprising:
reference lines;
select lines; and
data lines that are orthogonal to the select lines; and
a plurality of memory cells electrically connected to the reference lines, each memory cell including
a memory plug having a multi-resistive state material that has two terminals, the first terminal being electrically connected to one of the data lines; and
a transistor having
a source that is electrically connected to one of the reference lines;
a drain that is electrically connected to the second terminal of the memory plug; and
a gate that is electrically connected to one of the select lines
wherein the multi-resistive state material is a complex metal oxide.