Preservation circuit and methods to maintain values representing data in one or more layers of memory
View Patent ↗Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
1. A memory device comprising:
at least one layer of memory including a plurality of memory cells, each memory cell configured to store logic states associated with resistance values; and
a preservation circuit electrically coupled with the plurality of memory cells and configured to, in response to a trigger signal, restore the resistance values to represent the logic states,
wherein the preservation circuit is further configured to preserve the resistance values of a subset of the plurality of memory cells.
2. A computer-readable medium including executable instructions configured to perform steps comprising:
sleeping for a period of time;
determining a portion of memory to read, the memory including a plurality of resistive-based, nonvolatile memory cells;
reading the portion of the memory from a first location into a buffer; and
rewriting the portion of memory into a second location of the memory.
3. The computer-readable medium of claim 2 , wherein the sleeping for the period of time comprises sleeping for at least 500 milliseconds.
4. The computer-readable medium of claim 2 , wherein the second location comprises the first location.
5. The computer-readable medium of claim 2 , wherein the sleeping for the period of time further comprises operating a clock in a host to count a number of time units associated with the period of time.