Memory array of a non-volatile ram

1. A non-volatile RAM comprising:

a plurality of memory cells formed on a semiconductor substrate each cell capable of being selected through a select line and a data line, and having

a semiconductor device that controls current flow depending on the voltage of the select line;

a multi-resistive state material that

changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material;

changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse;

maintains the resistive state even if power ceases to be supplied to the memory cell; and

wherein

the resistive state of the memory cell determines the information stored in the memory cell;

at least one intermediary resistive state is used so that the memory cell is capable of storing more than one bit of information, whereby the multi-resistive state material is placed in the various resistive states through voltage pulses of varying magnitude, polarity, and/or duration;

the resistive range between the high resistive state and the low resistive state is substantially evenly subdivided by the at least one intermediary resistive state; and

the intermediary resistive state logarithmically subdivides the high resistive state and the low resistive state.

2. A non-volatile RAM memory of array that retains information in the absence of power, comprising:

a plurality of memory cells, each cell having

a multi-resistive state material that chances its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse, wherein the resistive state of the memory cell determines the information stored in the memory cell; and

a semiconductor device that controls current flow to the multi-resistive state material;

wherein

at least one intermediary resistive state is used so that the memory cell is capable of storing more than one bit of information, whereby the multi-resistive state material is placed in the various resistive states through voltage pulses of varying magnitude, polarity, and duration;

at least two intermediary resistive states are used whereby the memory cell is capable of storing at least two bits of information; and

the low resistive state is separated from the high resistive state by at least a factor of 10.

3. The non-volatile RAM memory of array of claim 2 , wherein the resistive range between the high resistive state and the low resistive state is substantially evenly subdivided by the intermediary resistive states.

4. The non-volatile RAM memory array of claim 3 , wherein the intermediary resistive state logarithmically subdivides the high resistive state and the low resistive state.

5. The non-volatile RAM memory of array of claim 2 , wherein the multi-resistive state material is capable of changing its resistive state by at least a factor of 100 upon application of a voltage pulse.

6. The non-volatile RAM memory of array of claim 5 , wherein the multi-resistive state material is capable of changing its resistive state by at least a factor of 1000 upon application of a voltage pulse.

7. A non-volatile RAM memory of array that retains information in the absence of power, comprising:

a plurality of memory cells, each cell having

a multi-resistive state material that chances its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse, wherein the resistive state of the memory cell determines the information stored in the memory cell; and

a semiconductor device that controls current flow to the multi-resistive state material;

wherein

at least one intermediary resistive state is used so that the memory cell is capable of storing more than one bit of information, whereby the multi-resistive state material is placed in the various resistive states through voltage pulses of varying magnitude, polarity, and duration;

at least six intermediary resistive states are used, whereby the memory cell is capable of storing at least three bits of information; and

the multi-resistive state material is capable of changing its resistive state by at least a factor of 100 upon application of a voltage pulse.

8. The non-volatile RAM memory of array of claim 7 , wherein the multi-resistive state material is capable of changing its resistive state by at least a factor of 1000 upon application of a voltage pulse.

9. A non-volatile RAM memory of array that retains information in the absence of power, comprising:

a plurality of memory cells, each cell having

a multi-resistive state material that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse, wherein the resistive state of the memory cell determines the information stored in the memory cell; and

a semiconductor device that controls current flow to the multi-resistive state material;

wherein

at least one intermediary resistive state is used so that the memory cell is capable of storing more than one bit of information, whereby the multi-resistive state material is placed in the various resistive states through voltage pulses of varying magnitude, polarity and duration;

at least fourteen intermediary resistive states are used, whereby the memory cell is capable of storing at least four bits of information; and

the multi-resistive state material is capable of changing its resistive state by at least a factor of 1000 upon application of a voltage pulse.

10. A non-volatile RAM memory of array that retains information in the absence of power, comprising:

a plurality of memory cells, each cell having

a multi-resistive state material that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse, wherein the resistive state of the memory cell determines the information stored in the memory cell; and

a semiconductor device that controls current flow to the multi-resistive state material;

wherein

at least one intermediary resistive state is used so that the memory cell is capable of storing more than one bit of information, whereby the multi-resistive state material is placed in the various resistive states through voltage pulses of varying magnitude, polarity, and duration; and

the low resistive state is separated from the high resistive state by at least a factor of 10.

11. A non-volatile RAM memory array comprising:

a semiconductor substrate

reference lines;

a plurality of memory cells electrically connected to the reference lines, each memory cell including

a transistor formed on the semiconductor; and

a memory plug having a multi-resistive state material element in electrical contact with the transistor;

select lines in electrical contact with the transistors; and

data lines that are orthogonal to the select lines and in electrical contact with either the transistors;

wherein the reference lines are parallel to the select lines and span two memory cells in the select line direction.

12. The non-volatile RAM memory array of claim 11 wherein the reference lines are formed on the first metallization layer above the semiconductor substrate.

13. The non-volatile RAM memory array of claim 12 wherein the data lines are formed on the second metallization layer above the semiconductor substrate.

14. The non-volatile RAM memory array of claim 11 wherein the select lines are a polysilicon material.

15. The non-volatile RAM memory array of claim 14 wherein the multi-resistive state material is a complex metal oxide.