Buffering systems methods for accessing multiple layers of memory in integrated circuits
View Patent ↗Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.
1. A method for accessing memory in an integrated circuit, comprising:
alternating selection of a first write buffer for loading and a second write buffer to write a first number of bits during a write cycle; and
alternating selection of a first read buffer and a second read buffer to read a second number of bits during a read cycle; and
decoding an address for accessing a number of third dimension memory cells to either write the first number of bits or read the second number of bits, the number of third dimension memory cells residing in at least one layer of multiple layers of the third dimension memory cells.
2. The method of claim 1 , wherein the decoding the address comprises
determining the at least one layer of multiple layers from at least a portion of the address, and
transmitting the first number of bits in a direction substantially orthogonal to the at least one layer of the multiple layers.
3. The method of claim 1 , wherein the first number of bits is different than the second number of bits.
4. The method of claim 1 , wherein the alternating selection of the first write buffer and the second write buffer comprises loading a number of bits into the first write buffer at a write data interface data rate that is substantially equivalent to a write speed at which the first number of bits is written.
5. The method of claim 1 and further comprising:
writing the first number of bits into the number of third dimension memory cells using a programming voltage having a slew rate over at least a portion of the write cycle; and
implementing the first number of bits as a size for the first write buffer and the second write buffer to maintain a write speed for the slew rate.
6. The method of claim 1 and further comprising:
implementing the first number of bits as a size for the first write buffer and the second write buffer to maintain compliance with respect to a peak power threshold.
7. A method for accessing memory in an integrated circuit, comprising:
determining a size for a plurality of write buffers as a function of a slew rate for a programming voltage; and
configuring a buffer controller to write to a layer constituting one of multiple layers of a memory from a first subset of the write buffers and to load a second subset of the write buffers,
wherein writing data from the first subset substantially overlaps an interval in which the second subset is loaded.
8. The method of claim 7 , wherein the determining the size comprises selecting the slew rate for writing to a plurality of third dimension memory cells disposed in the layer.
9. The method of claim 7 , wherein determining the size comprises selecting the size as a multiple of an amount of data bits being loaded at an interface data rate.
10. The method of claim 7 , wherein configuring the buffer controller comprises
setting a counter to count data bits until a number of the data bits that is loaded into the second subset of write buffers is equivalent to the size, and
configuring the buffer controller to switch the second subset of write buffers from loading to writing.
11. The method of claim 7 , wherein determining the size comprises
determining a size for a plurality of read buffers as a function of a read voltage, and
configuring the buffer controller to read from the multiple layers of memory into a first subset of the read buffers and a second subset of the read buffers,
wherein the size of each of plurality of read buffers is different than the size for the plurality of write buffers.
12. The method of claim 7 and further comprising:
detecting a write of a state to a memory cell storing the same state; and
preventing the write of the state to the memory cell.
13. The method of claim 12 , wherein detecting the write of the state comprises
reading a stored state in the memory cell,
comparing the stored state to the state associated with the write, and
disabling the write if there is a match between the stored state and the state associated with the write.
14. The method of claim 7 and further comprising:
configuring a write operation to include a read operation for at least one location in the memory;
comparing write data for the write operation to read data for the read operation; and
determining whether to disable the write operation to the at least one location.
15. The method of claim 14 , wherein the determining comprises disabling the write operation if the write data is substantially identical to the read data.