Serial memory interface
View Patent ↗A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configured to control access to the memory array by the plurality of serial ports, the logic block using the serial ports to transfer data between the memory array and at least one of the plurality of serial ports.
1. A memory system, comprising:
a partitioned memory army, each partition operable to be accessed independently;
a plurality of serial ports in data communication with the partitioned memory array; and
arbitration switch logic configured to control access to each partition of the partitioned memory array by the plurality of serial ports.
2. The memory system recited in claim 1 wherein the memory array is non-volatile.
3. The memory system recited in claim 1 , wherein the partitioned memory array is configured as a stacked cross point array.
4. The memory system recited in claim 1 wherein the partitioned memory array includes two-terminal memory elements that include an electrolytic tunnel barrier and a mixed valence conductive oxide.
5. The memory system recited in claim 1 , wherein each partition is a vertical plane.
6. The memory system recited in claim 1 , wherein each partition is a sub-plane.
7. The memory system recited in claim 1 , wherein each of the plurality of serial ports is configured to operate independently of other serial ports.
8. The memory system recited in claim 1 , wherein each of the plurality of serial ports is configured to access multiple partitioned memory arrays.
9. The memory system recited in claim 8 , wherein at least two of the plurality of serial ports are configured to cascade with each other.
10. The memory system recited in claim 1 , wherein the arbitration switch logic is configured to select one of the partitions of the partitioned memory array using packet data received by the plurality of serial ports.
11. The memory system recited in claim 10 , wherein packet data includes a control character configured to identify a data packet characteristic.
12. The memory system recited in claim 1 , wherein the arbitration switch logic controls access to each partition of the partitioned memory array by the plurality of serial ports by performing a priority select function.
13. The memory system recited in claim 1 and further comprising an encoder configured to encode data transferred over the plurality of serial ports.
14. The memory system recited in claim 1 and further comprising a physical layer logic module having a phased locked loop circuit that is shared by the plurality of serial ports.
15. The memory system recited in claim 1 , wherein one or more of the plurality of serial ports uses differential signaling.
16. The memory system recited in claim 1 , wherein the data is transferred according to a protocol used by the plurality of serial ports, the protocol enabling different data packets to be sent between the memory array and the plurality of serial ports.
17. A memory system, comprising:
a non-volatile memory array;
serial ports in data communication with the non-volatile memory array, wherein the serial ports are operable to send an access request to the non-volatile memory array; and
logic to connect the serial ports, where the serial ports can access the internal non-volatile memory or can pass a access requests from one serial port to another serial port,
wherein at least one serial port is operable to be connected to another memory system having a serial port that is in data communication with a non-volatile memory array.
18. The memory system recited in claim 17 , wherein at least one serial port is configured to cascade with another memory system having a serial port that is in data communication with a non-volatile memory array.
19. The memory system recited in claim 18 , wherein the cascaded ports can be accessed from two directions, whereby redundant paths are configured for an array of devices.
20. The memory system recited in claim 19 , wherein access requests are configurable to be routed in either of the two directions.
21. The memory system recited in claim 17 , further comprising arbitration logic to arbitrate routing corresponding to address information within the access request.
22. The memory system recited in claim 17 , wherein at least two serial ports are operable to be connected to at least two other memory systems, each memory system having a serial port that is in data communication with a non-volatile memory array.
23. The memory system recited in claim 22 , wherein at least three serial ports are operable to be connected to at least three other memory systems, each memory system having a serial port that is in data communication with a non-volatile memory array.
24. The memory system recited in claim 17 , wherein the memory device operates as a switch between multiple serial ports.
25. The memory device recited in claim 17 , wherein the non-volatile memory array stores configuration data that operable to set address assignments and muting permits.
26. The memory device recited in claim 17 , wherein separate memory systems may be accessed simultaneously.