IP Library Granted Patent US 6,870,755
Granted Patent B2
US 6,870,755 · App. 10/604,556 · Granted Mar 22, 2005

Re-writable memory with non-linear memory element

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Quick Facts
Patent No.
US 6,870,755
App. No.
10/604,556
Granted
Mar 22, 2005
Kind
B2
Abstract

A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.

Claims (45)

1. A 2-terminal re-writable memory cell, comprising:

a non-linear resistive memory element that can store non-volatile information;

wherein

the resistance of the non-linear resistive memory element can be reversibly written to different values, whereby the resistance of the non-linear resistive memory is used to determine the stored information; and

the memory cell is accessed through exactly 2 terminals.

2. The 2-terminal re-writable memory cell of claim 1 , wherein the non-linear resistive memory element includes a conductive metal oxide.

3. The 2-terminal re-writable memory cell of claim 2 , wherein the non-linear resistive element includes at least one electrode that interfaces with the conductive metal oxide.

4. The 2-terminal re-writable memory cell of claim 3 , wherein the non-linearity is induced at the interface between at least one electrode and the conductive metal oxide.

5. The 2-terminal re-writable memory cell of claim 4 , wherein the non-linear resistive element includes two electrodes that interface with the conductive metal oxide and the non-linearity is induced at the interfaces between electrodes and the conductive metal oxide.

6. The 2-terminal re-writable memory cell of claim 1 , wherein the non-linearity resistive element includes a resistive memory material and a non-linear device in series.

7. The 2-terminal re-writable memory cell of claim 6 , wherein the non-linear device includes two backward diodes back to back.

8. A re-writable memory comprising:

a plurality of x-direction conductive lines, each conductive line being patterned in a first direction;

a plurality of y-direction conductive lines, each conductive line being patterned in a second direction orthogonal to the first direction;

a plurality of memory cells, each memory cell being accessible for reading or writing through selection of an x-direction conductive line and a y-direction conductive line;

wherein

a memory cell is located at or near the intersection of the selected x-direction conductive array line and the selected y-direction conductive array line; and

the memory cells include a non-linear resistive element.

9. The re-writable memory of claim 8 , wherein:

the non-linear resistive element includes a resistive memory element and a non-ohmic device in series.

10. The re-writable memory of claim 9 , wherein:

the non-ohmic device includes two backward diodes back to back.

11. The re-writable memory of claim 8 , wherein:

the non-linear resistive memory element includes a conductive metal oxide and at least one electrode.

12. The re-writable memory of claim 11 , wherein:

the non-linear resistive memory element includes a conductive metal oxide and two electrodes.

13. A memory cell comprising:

a bottom electrode;

a top electrode; and

at least one conductive metal oxide sandwiched in-between the bottom and top electrodes;

wherein the memory cell exhibits a non-linear IV characteristic between the top and bottom electrodes.

14. The memory cell of claim 13 , wherein:

the write threshold of the memory element is fabricated to match the non-linear IV characteristic of the memory cell.

15. The memory cell of claim 14 , wherein:

the write threshold of the memory element is less than the non-ohmic voltage of the memory cell.

16. A memory cell, comprising:

a first terminal that is capable of being placed at a first voltage potential;

a non-linear device that is electrically coupled to the first terminal;

a non-volatile resistive memory element that is electrically coupled to the non-linear device; and

a second terminal that is capable of being placed at a second voltage potential and is electrically coupled to the non-volatile resistive memory element;

wherein the resistance of the non-volatile resistive memory element can be reversibly written to different values, whereby the resistance of the non-volatile resistive memory is used to determine the stored information.

17. The memory cell of claim 16 , wherein:

the non-linear device includes an electrode that interfaces with the non-volatile memory element, such that the non-linearity is induced at the interface between at least one electrode and the conductive metal oxide.

18. The memory cell of claim 16 , wherein:

the non-linear device includes two backward diodes in opposite directions and in series.

Assignments (4)
RELEASE Recorded Apr 9, 2012
From: SILICON VALLEY BANK; GOLD HILL CAPITAL
To: UNITY SEMICONDUCTOR, INC.
Reel/Frame 028132/0675 →
SECURITY AGREEMENT Recorded Apr 13, 2009
From: UNITY SEMICONDUCTOR CORPORATION
To: GOLD HILL CAPITAL
Reel/Frame 023129/0669 →
MERGER Recorded Jul 28, 2005
From: UNITY SEMICONDUCTOR CORPORATION
To: UNITY SEMICONDUCTOR CORPORATION
Reel/Frame 016323/0107 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2003
From: RINERSON, DARRELL; CHEVALLIER, CHRISTOPHE J.; LONGCOR, STEVEN W.; KINNEY, WAYNE; WARD, EDMOND R.; HSIA, STEVE KUO-REN
To: UNITY SEMICONDUCTOR CORPORATION
Reel/Frame 013857/0935 →