1T-1R architecture for resistive random access memory
A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.
1. A memory device comprising:
an array of memory cells arranged in a plurality of columns in a first direction and a plurality of rows in a second direction, wherein each memory cell in the array comprises:
a select transistor, wherein a source terminal of the select transistor is coupled to a source line, and wherein a gate terminal of the select transistor is coupled to a word line, the source line to receive an unselected source line voltage that is higher than a ground potential when a corresponding memory cell is not selected for an operation, wherein the unselected source line voltage is received before a selected word line voltage is received at the word line for a corresponding selected memory cell; and
a memory element coupled in series with the select transistor, wherein a first end of the memory element is coupled to a drain terminal of the select transistor, and wherein a second end of the memory element is coupled to a bit line.
2. The memory device of claim 1 , wherein each memory cell in one of the plurality of columns shares a first common bit line and wherein each memory cell in one of the plurality of rows shares a first common word line and first common source line.
3. The memory device of claim 1 , wherein memory cells positioned on adjacent rows of the array are electrically coupled to receive a common source line signal.
4. The memory device of claim 1 , further comprising:
a control circuit to generate source line signals, word line signals and bit line signals to control operation of the memory array.
5. The memory device of claim 4 , wherein the control circuit to apply a selected source line voltage to a selected source line corresponding to a selected memory cell of the array that is selected for the operation.
6. The memory device of claim 5 , wherein the control circuit to apply the unselected source line voltage that is different from the selected source line voltage to unselected source lines corresponding to unselected memory cells of the array that are not selected for the operation.
7. The memory device of claim 6 , wherein the unselected source line voltage is higher than the selected source line voltage.
8. The memory device of claim 6 , wherein the unselected source line voltage is lower than a selected bit line voltage.
9. A method comprising:
selecting a memory cell of an array of memory cells;
applying a selected source line voltage to a selected source line corresponding to a selected memory cell that is selected for an operation;
applying an unselected source line voltage that is higher than a ground potential and different from the selected source line voltage to unselected source lines corresponding to unselected memory cells that are not selected for the operation, wherein the unselected source line voltage is applied before a selected word line voltage is applied to a selected word line for a corresponding selected memory cell; and
performing the operation on the selected memory cell.
10. The method of claim 9 , wherein the unselected source line voltage is higher than the selected source line voltage.
11. The method of claim 9 , wherein the unselected source line voltage is lower than a selected bit line voltage.
12. The method of claim 9 , wherein each memory cell in the array comprises:
a select transistor, wherein a source terminal of the select transistor is coupled to a source line, and wherein a gate terminal of the select transistor is coupled to a word line; and
a memory element coupled in series with the select transistor, wherein a first end of the memory element is coupled to a drain terminal of the select transistor, and wherein a second end of the memory element is coupled to a bit line.
13. The method of claim 12 , wherein each memory cell in one of a plurality of columns in the array shares a first common bit line and wherein each memory cell in one of a plurality of rows in the array shares a first common word line and first common source line.
14. A memory device, comprising:
a plurality of word lines;
a plurality of source lines;
a plurality of bit lines; and
an array of resistive memory cells, each resistive memory cell in the array comprising:
a select transistor, wherein a source terminal of the select transistor is coupled to one of the plurality of source lines, and wherein a gate terminal of the select transistor is coupled to one of the plurality of word lines, the one of the plurality of source lines to receive an unselected source line voltage that is higher than a ground potential when a corresponding resistive memory cell is not selected for an operation, wherein the unselected source line voltage is received before a selected word line voltage is received at a word line for a corresponding selected memory cell; and
a memory element coupled in series with the select transistor, wherein a first end of the memory element is coupled to a drain terminal of the select transistor, and wherein a second end of the memory element is coupled to one of the plurality of bit lines.
15. The memory device of claim 14 , wherein selected source lines of the plurality of source lines corresponding to selected resistive memory cells are to receive a selected source line voltage.
16. The memory device of claim 15 , wherein unselected source lines of the plurality of source lines corresponding to unselected resistive memory cells are to receive the unselected source line voltage that is different from the selected source line voltage.
17. The memory device of claim 14 , wherein the resistive memory cells of the array are arranged in a plurality of columns in a first direction and a plurality of rows in a second direction.
18. The memory device of claim 17 , wherein each restive memory cell in one of the plurality of columns shares a first common bit line and wherein each memory cell in one of the plurality of rows shares a first common word line and first common source line.