Multi-layered conductive metal oxide structures and methods for facilitating enhanced performance characteristics of two-terminal memory cells
A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.
1. A memory cell comprising:
a metal oxide semiconductor field effect transistor (MOSFET) select transistor; and
a memory element coupled to the MOSFET select transistor, the memory element comprising:
a first electrode;
a first layer of conductive metal oxide (CMO) on a first surface of the first electrode, the first layer of CMO being a reservoir for mobile oxygen ions;
a second layer of CMO having similarly-dimensioned crystalline structures as the first layer of CMO on a first surface of the first layer of CMO; and
an element implanted at a depth through the second layer of CMO to reach a portion of the first layer of CMO to form an ion obstruction barrier.
2. The memory cell of claim 1 , wherein the first electrode is formed on a substantially planar upper surface of an electrically conductive support layer.
3. The memory cell of claim 1 , wherein the memory element further comprises:
a layer of insulating metal oxide (IMO) on a second surface of the second layer of CMO.
4. The memory cell of claim 3 , wherein one or more of the layer of IMO, the first layer of CMO, or the second layer of CMO is formed in whole or in part using atomic layer deposition (ALD).
5. The memory cell of claim 3 , wherein the memory element further comprises:
a second electrode formed on a first surface of the layer of IMO.
6. The memory cell of claim 3 , wherein the ion obstruction barrier is configured to inhibit transport of other mobile ions between the first layer of CMO and the layer of IMO.
7. The memory cell of claim 6 , wherein the other mobile ions comprise metal cations.
8. An integrated circuit comprising:
an array of memory cells arranged in a plurality of columns in a first direction and a plurality of rows in a second direction, wherein each memory cell in the array comprises:
a metal oxide semiconductor field effect transistor (MOSFET) select transistor; and
a memory element coupled to the MOSFET select transistor, the memory element comprising:
a first electrode;
a first layer of conductive metal oxide (CMO) on a first surface of the first electrode, the first layer of CMO being a reservoir for mobile oxygen ions;
a second layer of CMO having similarly-dimensioned crystalline structures as the first layer of CMO on a first surface of the first layer of CMO; and
an element implanted at a depth through the second layer of CMO to reach a portion of the first layer of CMO to form an ion obstruction barrier.
9. The integrated circuit of claim 8 , wherein the first electrode is formed on a substantially planar upper surface of an electrically conductive support layer.
10. The integrated circuit of claim 8 , wherein the memory element further comprises:
a layer of insulating metal oxide (IMO) on a second surface of the second layer of CMO.
11. The integrated circuit of claim 10 , wherein one or more of the layer of IMO, the first layer of CMO, or the second layer of CMO is formed in whole or in part using atomic layer deposition (ALD).
12. The integrated circuit of claim 10 , wherein the memory element further comprises:
a second electrode formed on a first surface of the layer of IMO.
13. The integrated circuit of claim 10 , wherein the ion obstruction barrier is configured to inhibit transport of other mobile ions between the first layer of CMO and the layer of IMO.
14. The integrated circuit of claim 13 , wherein the other mobile ions comprise metal cations.
15. A memory device comprising:
a plurality of word lines;
a plurality of source lines;
a plurality of bit lines; and
an array of resistive memory cells, each resistive memory cell in the array comprising:
a metal oxide semiconductor field effect transistor (MOSFET) select transistor; and
a memory element coupled to the MOSFET select transistor, the memory element comprising:
a first electrode;
a first layer of conductive metal oxide (CMO) on a first surface of the first electrode, the first layer of CMO being a reservoir for mobile oxygen ions;
a second layer of CMO having similarly-dimensioned crystalline structures as the first layer of CMO on a first surface of the first layer of CMO; and
an element implanted at a depth through the second layer of CMO to reach a portion of the first layer of CMO to form an ion obstruction barrier.
16. The memory device of claim 15 , wherein the first electrode is formed on a substantially planar upper surface of an electrically conductive support layer.
17. The memory device of claim 15 , wherein the memory element further comprises:
a layer of insulating metal oxide (IMO) on a second surface of the second layer of CMO.
18. The memory device of claim 17 , wherein one or more of the layer of IMO, the first layer of CMO, or the second layer of CMO is formed in whole or in part using atomic layer deposition (ALD).
19. The memory device of claim 17 , wherein the memory element further comprises:
a second electrode formed on a first surface of the layer of IMO.
20. The memory device of claim 17 , wherein the ion obstruction barrier is configured to inhibit transport of other mobile ions between the first layer of CMO and the layer of IMO.