Multi-layered conductive metal oxide structures and methods for facilitating enhanced performance characteristics of two-terminal memory cells
A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.
1. A method of forming a two-terminal non-volatile re-writeable resistive memory element, comprising:
depositing an electrode;
forming a first layer of conductive metal oxide (CMO) on a first surface of the electrode, the first layer of CMO being a reservoir for mobile oxygen ions;
forming a second layer of CMO having similarly-dimensioned crystalline structures as the first layer of CMO on a second surface of the first layer of CMO; and
ion implanting an element at a depth through the second layer of CMO to reach a portion of the first layer of CMO to form an ion obstruction barrier.
2. The method of claim 1 , wherein forming the second layer of CMO comprises forming the second layer of CMO at a thickness from about 10 Angstroms to about 20 Angstroms.
3. The method of claim 1 , further comprising:
forming a layer of insulating metal oxide (IMO) on a third surface of the second layer of CMO.
4. The method of claim 3 , wherein the ion obstruction barrier is configured to inhibit transport of other mobile ions between the first layer of CMO and a layer of insulating metal oxide (IMO), wherein a selected one or more of the layer of IMO, the first layer of CMO, or the second layer of CMO are formed in whole or in part using atomic layer deposition (ALD).
5. The method of claim 4 , wherein the other mobile ions comprise metal cations.
6. The method of claim 1 , wherein the electrode is formed on a substantially planar upper surface of an electrically conductive support layer.
7. A two-terminal non-volatile re-writeable resistive memory element comprising:
an electrode;
a first layer of conductive metal oxide (CMO) on a first surface of the electrode, the first layer of CMO being a reservoir for mobile oxygen ions;
a second layer of CMO having similarly-dimensioned crystalline structures as the first layer of CMO on a second surface of the first layer of CMO; and
an element implanted at a depth through the second layer of CMO to reach a portion of the first layer of CMO to form an ion obstruction barrier.
8. The two-terminal non-volatile re-writeable resistive memory element of claim 7 , wherein the second layer of CMO comprises a thickness from about 10 Angstroms to about 20 Angstroms.
9. The two-terminal non-volatile re-writeable resistive memory element of claim 7 , further comprising:
a layer of insulating metal oxide (IMO) on a third surface of the second layer of CMO.
10. The two-terminal non-volatile re-writeable resistive memory element of claim 9 , wherein the ion obstruction barrier is configured to inhibit transport of other mobile ions between the first layer of CMO and a layer of insulating metal oxide (IMO), wherein a selected one or more of the layer of IMO, the first layer of CMO, or the second layer of CMO are formed in whole or in part using atomic layer deposition (ALD).
11. The two-terminal non-volatile re-writeable resistive memory element of claim 10 , wherein the other mobile ions comprise metal cations.
12. The two-terminal non-volatile re-writeable resistive memory element of claim 7 , wherein the electrode is formed on a substantially planar upper surface of an electrically conductive support layer.
13. A integrated circuit comprising:
an array of memory cells arranged in a plurality of columns in a first direction and a plurality of rows in a second direction, wherein each memory cell in the array comprises:
an electrode;
a first layer of conductive metal oxide (CMO) on a first surface of the electrode, the first layer of CMO being a reservoir for mobile oxygen ions;
a second layer of CMO having similarly-dimensioned crystalline structures as the first layer of CMO on a second surface of the first layer of CMO; and
an element implanted at a depth through the second layer of CMO to reach a portion of the first layer of CMO to form an ion obstruction barrier.
14. The integrated circuit of claim 13 , wherein the second layer of CMO comprises a thickness from about 10 Angstroms to about 20 Angstroms.
15. The integrated circuit of claim 13 , further comprising:
a layer of insulating metal oxide (IMO) on a third surface of the second layer of CMO.
16. The integrated circuit of claim 15 , wherein the ion obstruction barrier is configured to inhibit transport of other mobile ions between the first layer of CMO and a layer of insulating metal oxide (IMO), wherein a selected one or more of the layer of IMO, the first layer of CMO, or the second layer of CMO are formed in whole or in part using atomic layer deposition (ALD).
17. The integrated circuit of claim 16 , wherein the other mobile ions comprise metal cations.
18. The integrated circuit of claim 13 , wherein the electrode is formed on a substantially planar upper surface of an electrically conductive support layer.
19. The integrated circuit of claim 13 , wherein the first layer of CMO and the second layer of CMO comprise different compositions based on at least one of different elements, different stoichiometries, or different concentrations of oxygen ions.
20. The integrated circuit of claim 13 , wherein each memory cell further comprises crystalline orientations and sizes of grains in the first layer of CMO that are replicated in the second layer of CMO.