Planar resistive memory integration
View Patent ↗In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.
1. A method, comprising:
providing a dielectric layer;
forming a void in the dielectric layer; and
forming a structure in the void, the structure comprising:
a first layer of memory material;
an interconnect above the first layer of memory material; and
a second layer of memory material above the interconnect.
2. The method of claim 1 , wherein the structure further comprises an insulating metal oxide (IMO) layer formed in the void below the interconnect.
3. The method of claim 2 , wherein the IMO layer comprises at least one of hafnium oxide or tantalum oxide.
4. The method of claim 1 , further comprising:
forming a word line; and
forming the dielectric layer above the word line;
wherein said void in the dielectric layer exposes a portion of an upper surface of the word line.
5. The method of claim 4 , wherein the word line is orthogonal with respect to a conductive line of the interconnect.
6. The method of claim 1 , wherein said void comprises a trench.
7. The method of claim 1 , wherein said void comprises a via.
8. The method of claim 1 , forming another structure above the void, the another structure comprising:
a third layer of memory material;
another interconnect above the third layer of memory material; and
a fourth layer of memory material above the another interconnect.
9. The method of claim 8 , wherein a conductive line of the another interconnect is orthogonal with respect to a conductive line of the interconnect.
10. The method of claim 1 , wherein the structure comprises a portion of a first two-terminal resistive memory element and a portion of a second two-terminal resistive memory element.
11. The method of claim 1 , further comprising:
depositing insulating metal oxide and conductive metal oxide above a word line; and
performing a planarization after the deposition.
12. The method of claim 11 , further comprising:
performing a recessing of the deposited conductive metal oxide after the planarization; and
forming a low oxidation electrode at least partially in the recess.
13. The method of claim 12 , further comprising:
depositing the insulating metal oxide and the conductive metal oxide above the interconnect; and
performing another planarization after depositing the insulating metal oxide and the conductive metal oxide above the interconnect.
14. The method of claim 1 , further comprising:
forming an IMO layer above the void; and
forming a low oxidization electrode above the IMO layer that is formed above the void.
15. The method of claim 14 , wherein the low oxidation electrode above the insulating metal oxide layer that is formed above the void comprises a line oriented orthogonally to a word line formed below the void.
16. The method of claim 15 , wherein the IMO layer comprises at least one of hafnium oxide or tantalum oxide.
17. The method of claim 1 , wherein the first layer of memory material comprises at least one layer of a conductive metal oxide (CMO).
18. An apparatus, comprising:
a dielectric layer;
a recess formed in the dielectric layer, the recess having a bottom and a top edge and a planar sidewall extending from the bottom to the top edge;
a portion of a first two-terminal resistive memory cell located within the recess;
a portion of a second two-terminal resistive memory cell located above the first two-terminal resistive memory cell and within the recess,
wherein the portion of the second two-terminal resistive memory cell that is located within the recess is electrically connected to the portion of the first two-terminal memory cell that is located within the recess by a conductive material formed in the recess.
19. The apparatus of claim 18 , wherein the portion of the first two-terminal resistive memory cell comprises a first layer of memory material, and the portion of the second two-terminal resistive memory cell comprises a second layer of memory material.
20. The apparatus of claim 19 , wherein the portion of the first two-terminal resistive memory cell further comprises an insulating metal oxide (IMO) layer.
21. The apparatus of claim 20 , wherein the first layer of memory material comprises at least one layer of a conductive metal oxide (CMO).
22. The apparatus of claim 21 , wherein the IMO layer comprises at least one of hafnium oxide or tantalum oxide.
23. The apparatus of claim 22 , further comprising an IMO layer located above the recess.