IP Library Granted Patent US 7,875,518
Granted Patent B2
US 7,875,518 · App. 12/453,737 · Granted Jan 25, 2011

Semiconductor device having silicon layer in a gate electrode

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Quick Facts
Patent No.
US 7,875,518
App. No.
12/453,737
Granted
Jan 25, 2011
Kind
B2
Abstract

A method for forming a semiconductor device includes, in order, consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate, implanting boron into the silicon layer, diffusing the boron by heat-treating the silicon layer, implanting phosphorous into the silicon layer, diffusing at least the phosphorous by heat-treating the silicon layer, and patterning the silicon layer by using a dry etching technique.

Claims (52)

1. A method for forming a semiconductor device comprising:

consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate;

implanting boron into said silicon layer;

after the implanting of the boron, diffusing said boron by heat-treating said silicon layer;

implanting phosphorous into said silicon layer;

diffusing at least said phosphorous by heat-treating said silicon layer; and

after the diffusing of at least the phosphorous, patterning said silicon layer by using a dry etching technique.

2. The method according to claim 1 , wherein said diffusing said boron is conducted at a temperature of not less than 900° C.

3. The method according to claim 1 , wherein said diffusing at least said phosphorous is conducted at a temperature of not lower than 900° C.

4. A method for forming a semiconductor device comprising in order:

consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate;

implanting boron into said silicon layer;

diffusing said boron by heat-treating said silicon layer;

implanting phosphorous into said silicon layer;

diffusing at least said phosphorous by heat-treating said silicon layer;

depositing a metal layer including a high-melting-point metal on said silicon layer;

forming a film pattern including silicon nitride on said metal layer; and

patterning said silicon layer by using a dry etching technique,

wherein said patterning said silicon layer uses said film pattern as a mask and additionally patterns said metal layer.

5. A method for forming a semiconductor device comprising:

consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate;

implanting phosphorous into said silicon layer;

after the implanting of the phosphorous, diffusing said phosphorous by heat-treating said silicon layer;

implanting boron into said silicon layer;

diffusing at least said boron by heat-treating said silicon layer; and

after the diffusing of at least the boron, patterning said silicon layer by using a dry etching technique.

6. The method according to claim 5 , wherein said diffusing at least said boron is conducted at a temperature of not less than 900° C.

7. The method according to claim 5 , wherein said diffusing said phosphorous is conducted at a temperature of not less than 900° C.

8. A method for forming a semiconductor device comprising in order:

consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate;

implanting phosphorous into said silicon layer;

diffusing said phosphorous by heat-treating said silicon layer;

implanting boron into said silicon layer;

diffusing at least said boron by heat-treating said silicon layer;

depositing a metal layer including a high-melting-point metal on said silicon layer;

forming a film pattern including silicon nitride on said metal layer; and

patterning said silicon layer by using a dry etching technique,

wherein said patterning said silicon layer uses said film pattern as a mask and additionally patterns said metal layer.

9. The method according to claim 1 , wherein the silicon layer has a round bottom edge after the using of the dry etching technique.

10. The method according to claim 1 , wherein a ratio of a maximum boron concentration to a minimum boron concentration in a boron concentration profile across a thickness of the silicon layer is less than or equal to 100.

11. The method according to claim 10 , wherein a boron concentration is uniform in the boron concentration profile across the thickness of the silicon layer.

12. The method according to claim 1 , wherein a difference between a dosage of the phosphorus implanted per unit thickness and a dosage of the boron implanted per unit thickness in an n-type region of the silicon layer is greater than or equal to 1×10 20 cm −3 .

13. The method according to claim 10 , wherein the ratio of the maximum boron concentration to the minimum boron concentration in the boron concentration profile across the thickness of the silicon layer is in a range of 80 to 100.

14. The method according to claim 1 , further comprising, between the diffusing the boron and the implanting the phosphorous:

forming a photoresist pattern to cover p-type regions of the silicon layer and expose n-type regions of the silicon layer.

15. The method according to claim 1 , further comprising, between the diffusing of at least the phosphorous and the patterning of the silicon layer:

depositing a metal layer including a high-melting-point metal over the silicon layer.

16. The method according to claim 1 , further comprising, between the diffusing of at least the phosphorous and the patterning of the silicon layer:

forming a film pattern including silicon nitride over a metal layer deposited over the silicon layer.

17. The method according to claim 16 , wherein the patterning of the silicon layer uses the film pattern as a mask and additionally patterns the metal layer.

18. The method according to claim 15 , wherein the patterning of the silicon layer uses a film pattern as a mask and additionally patterns the metal layer.

19. The method according to claim 1 , wherein the patterning of the silicon layer uses a film pattern as a mask and additionally patterns a metal layer deposited over the silicon layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2018
From: RAMBUS INC.
To: HEFEI RELIANCE MEMORY LIMITED
Reel/Frame 045984/0845 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2013
From: ELPIDA MEMORY, INC.
To: RAMBUS INC.
Reel/Frame 030049/0831 →