Manufacturing method for increasing product yield of memory devices suffering from source/drain junction leakage
View Patent ↗A DRAM device includes contact pads having a bottom in contact with a corresponding source/drain region 21 and a top in contact with a bottom of an overlying contact plug. The source/drain region has a recess caused by misalignment of the contact pad with respect to the source/drain region, the recess causing division of the original source/drain region. An additional diffused region is formed by ion-implantation to couple the divided source/drain region to reduce the junction leakage current flowing across the source/drain region.
1. A method for manufacturing a semiconductor device comprising:
forming a plurality gate electrode structures overlying a semiconductor substrate;
implanting impurities in a portion of said semiconductor substrate to form source/drain regions in association with said gate electrode structures;
depositing a conductive film on said source/drain regions by self-alignment process using said gate electrode structures as a mask;
patterning said conductive film by using a photoresist mask pattern to form a plurality of contact pads each in contact with a corresponding one of said source/drain regions,
wherein a misalignment of said photoresist mask in said patterning forms a recess on said semiconductor substrate; and
introducing impurities into a portion of said source/drain regions by a self-alignment process using said contact pads as a mask,
wherein in said introducing impurities, said impurities are introduced only into said recess.
2. The method according to claim 1 , wherein said introducing impurities includes implanting ions of said impurities into said portion of said semiconductor substrate.
3. The method according to claim 1 , wherein said introducing impurities includes solid-phase diffusing impurities contained in an interlevel dielectric film covering said contact pads into said portion of said semiconductor substrate.
4. The method according to claim 1 , wherein in said introducing impurities, said impurities are introduced into a recess of said semiconductor substrate formed by said patterning.
5. The method according to claim 4 , wherein said impurities introduced in said introducing impurities include phosphor.
6. The method according to claim 1 wherein in said introducing impurities, said impurities are introduced only into a portion of said source/drain regions which is not in contact with said contact pads.
7. The method according to claim 1 , wherein said portion of said source/drain regions is exposed from the photoresist mask pattern.
8. The method according to claim 1 , wherein in said introducing impurities, said impurities are not introduced through said contact pads.
9. The method according to claim 1 , wherein in said introducing impurities, said impurities do not pass through said implanted impurities.
10. The method according to claim 1 , wherein a portion of an upper surface of said impurities introduced by said introducing impurities is exposed.
11. The method according to claim 1 , wherein an exposed upper surface of said impurities introduced by said introducing impurities is not in contact with said implanted impurities.
12. The method according to claim 1 , wherein an entire area of a lower surface of said implanted impurities is not in contact with said impurities introduced by said introducing impurities.
13. The method according to claim 1 , wherein a portion of a lower surface of said implanted impurities is in contact with a surface portion of said semiconductor substrate.
14. A method for manufacturing a semiconductor device comprising:
forming a plurality gate electrode structures overlying a semiconductor substrate;
implanting impurities into a portion of said semiconductor substrate to form source/drain regions in association with said gate electrode structures;
depositing a conductive film on said source/drain regions by a self-alignment process using said gate electrode structures as a mask;
patterning said conductive film by using a photoresist mask pattern to form a plurality of contact pads each in contact with a corresponding one of said source/drain regions,
wherein said patterning comprises an etching,
wherein a misalignment in said patterning forms a recess by said etching on said semiconductor substrate; and
introducing impurities into a portion of said source/drain regions by a self-alignment process using said contact pads as a mask,
wherein said recess divides said implanted impurities into two parts, and
wherein said introduced impurities couples together said divided implanted impurities.
15. A method of manufacturing a semiconductor device comprising:
forming a plurality of gate electrode structures overlying a semiconductor substrate;
implanting impurities into a portion of said semiconductor substrate to form source/drain regions in association with said gate electrode structures;
depositing a conductive film on said source/drain regions by a self-alignment process using said gate electrode structures as a mask;
patterning said conductive film by using a photoresist mask pattern and etching to form a plurality of contact pads each in contact with a corresponding one of said source/drain regions,
wherein a misalignment in said patterning forms a recess by said etching on said semiconductor substrate, said recess dividing said implanted impurities into two separate parts; and
introducing impurities into a portion of said source/drain regions by a self-alignment process using said contact pads as a mask,
wherein said introduced impurities couple together said divided implanted impurities.