Semiconductor chip having pollished and ground bottom surface portions
View Patent ↗A semiconductor chip having a thickness of 130 micrometers or less includes a mechanically ground bottom surface corresponding to a central circuit area, and a polished bottom surface corresponding to a peripheral scribe area. The mechanically ground bottom surface prevents heavy metals attached onto the bottom surface of the wafer from diffusing toward the source/drain regions of the semiconductor substrate and thereby from degrading the transistor characteristics.
1. A semiconductor device, comprising a diced semiconductor chip including a central circuit area having a semiconductor active layer and a peripheral scribe area, said peripheral scribe area encircling and contacting an entire circumference of said central circuit area, said peripheral scribe area having a bottom surface having a surface roughness lower than a surface roughness of a bottom surface of said central circuit area.
2. The semiconductor device according to claim 1 , wherein said diced semiconductor chip has a thickness not larger than 130 micrometers.
3. The semiconductor device according to claim 1 , wherein said bottom surface of said peripheral scribe area comprises a polished surface, and said bottom surface of said central scribe area comprises a mechanically ground surface.
4. The semiconductor device according to claim 3 , wherein said bottom surface of said central circuit area has a central-line surface average roughness not lower than 50 nm, and said bottom surface of said peripheral scribe area has a central-line surface average roughness lower than 50 nm.
5. The semiconductor device according to claim 1 wherein said semiconductor device comprises a semiconductor memory device.
6. A silicon wafer, comprising:
a silicon substrate; and
a plurality of semiconductor packages formed on the silicon substrate,
wherein a bottom surface of the silicon substrate is ground and a peripheral scribe area encircling an entire circumference of each of the plurality of semiconductor packages on the bottom surface of the silicon substrate is polished to a polished fine surface, and
wherein the bottom surface of the silicon substrate area has a central-line surface average roughness not lower than 50 nm, and the bottom surface of the peripheral scribe area has a central-line surface average roughness lower than 50 nm.
7. The silicon wafer of claim 6 , further comprising a protective sheet bonded to the bottom surface of the silicon substrate.
8. The silicon wafer of claim 6 , further comprising a protective sheet associated with a top surface of the silicon substrate.
9. The silicon wafer of claim 6 , wherein the semiconductor packages comprise:
a plurality of transistors associated with the silicon substrate;
a plurality of interconnections associated with the silicon substrate; and
a plurality of interlevel dielectric films associated with the silicon substrate, the interconnections, and the transistors.
10. The silicon wafer of claim 9 , wherein the plurality of transistors comprise metal insulator-semiconductor transistors.
11. The silicon wafer of claim 6 , further comprising a protective film formed on the semiconductor packages.
12. The silicon wafer of claim 6 , wherein the plurality of semiconductor packages comprise a dynamic random access memory.
13. The silicon wafer of claim 6 , wherein the plurality of semiconductor packages comprise a fine-pitch ball-grid-array multichip package.
14. The silicon wafer of claim 6 , wherein the peripheral scribe area has a polished thickness of 2 micrometers.