Semiconductor device comprising a bipolar transistor
A semiconductor device comprising a bipolar transistor and a method of making the same. The bipolar transistor includes a collector having a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a reduced surface field (RESURF) gate located above an upper surface of the laterally extending drift region for shaping an electric field within the collector. The bipolar transistor further includes a gap located between the reduced surface field gate and an extrinsic region of the base of the device, for electrically isolating the reduced surface field gate from the base. A lateral dimension L gap of the gap is in the range 0.1 μm≦L gap ≦1.0 μm.
1. A semiconductor device comprising a bipolar transistor, the bipolar transistor comprising:
a collector having a laterally extending drift region;
a base located above the collector, wherein an extrinsic region of the base at least partially surrounds an intrinsic region of the base that is located above an upper surface of the laterally extending drift region;
an emitter located above the base;
a reduced surface field (RESURF) gate located above the upper surface of the laterally extending drift region for shaping an electric field within the collector; and
a gap located between the reduced surface field gate and the extrinsic region of the base of the device, and filled with a dielectric material for electrically isolating the reduced surface field gate from the base,
wherein a lateral dimension L gap of the gap is in the range 0.1 μm≦L gap ≦1.0 μm.
2. The semiconductor device of claim 1 , wherein a lateral distance L d between the reduced surface field (RESURF) gate and an emitter window of the device is in the range 0.2 μm≦L d ≦1.2 μm.
3. The semiconductor device of claim 1 , wherein L gap <0.5 μm.
4. The semiconductor device of claim 3 , wherein a lateral distance L d between the reduced surface field (RESURF) gate and an emitter window of the device is in the range 0.2 μm≦L d <0.6 μm.
5. The semiconductor device of claim 3 , wherein L gap ≦0.2 μm.
6. The semiconductor device of claim 5 , wherein a lateral distance L d between the reduced surface field (RESURF) gate and an emitter window of the device is in the range 0.2 μm≦L d ≦0.3 μm.
7. The semiconductor device of claim 1 , wherein the reduced surface field gate includes a monocrystalline doped semiconductor portion in contact with the upper surface of the laterally extending drift region, wherein the monocrystalline doped semiconductor portion has a different conductivity type to that of the collector whereby a junction is formed at an interface between the monocrystalline doped semiconductor portion and the laterally extending drift region.
8. The semiconductor device of claim 7 further comprising:
a doped polysilicon layer located above the monocrystalline doped semiconductor portion, wherein the doped polysilicon layer corresponds to the extrinsic region of the base, and
a layer located between the doped polysilicon layer and the monocrystalline doped semiconductor portion, for preventing dopants from the doped polysilicon layer entering the monocrystalline doped semiconductor portion.
9. The semiconductor device of claim 1 , wherein the reduced surface field gate comprises a field plate separated from the upper surface of the laterally extending drift region by a dielectric.
10. The semiconductor device of claim 1 , comprising a further doped region having a conductivity type that is different to that of the collector, the further doped region extending laterally beneath the collector to form a junction at a region of contact between the further doped region and the collector.
11. A power amplifier comprising the semiconductor device of claim 1 .
12. A method of making a semiconductor device comprising a bipolar transistor, the method comprising:
providing a semiconductor substrate;
forming a collector on the substrate, the collector having a laterally extending drift region;
forming a base above the collector, wherein an extrinsic region of the base at least partially surrounds an intrinsic region of the base that is located above an upper surface of the laterally extending drift region;
forming an emitter above the base;
forming a reduced surface field (RESURF) gate above the upper surface of the laterally extending drift region for shaping an electric field within the collector; and
etching a gap between the reduced surface field gate and the extrinsic region of the base of the device, and filling the gap with a dielectric material for electrically isolating the reduced surface field gate from the base,
wherein a lateral dimension L gap of the gap is in the range 0.1 μm≦L gap ≦1.0 μm.
13. The method of claim 12 , wherein a lateral distance L d between the reduced surface field (RESURF) gate and an emitter window of the device is in the range 0.2 μm≦L d ≦1.2 μm.
14. The method of claim 12 , wherein L gap <0.5 μm, and wherein the method further includes:
depositing a dielectric layer over the emitter, wherein an edge of the dielectric layer defines a first edge of the gap;
depositing a photoresist layer, wherein the photoresist layer includes an opening through which the edge of the dielectric layer defining the first edge of the gap is exposed and wherein an edge of the opening opposite the edge of the dielectric layer defines a second edge of the gap; and
etching said gap.
15. The method of claim 14 , wherein after the gap is etched, an edge of the emitter proximal the gap is vertically aligned with an edge of the extrinsic region of the base proximal the gap.