Packaged semiconductor device with interior polygonal pads
Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.
1. A semiconductor device comprising:
a semiconductor chip;
a package structure defining a rectangular boundary and having a bottom surface and comprising;
only two interior polygonal pads exposed at the bottom surface of the package structure, each of the two interior polygonal pads being located on a centerline of the bottom surface of the package structure; and
only six edge polygonal pads exposed at the bottom surface of the package structure, each of the six edge polygonal pads being located at an edge of the rectangular boundary, the six edge polygonal pads including one edge polygonal pad in the vicinity of each corner of the rectangular boundary;
wherein each of the two interior polygonal pads has a first side that is parallel to a facing side of the edge polygonal pad that is nearest to the first side and a second side that is parallel to a facing side of the edge polygonal pad that is nearest to the second side; and
wherein the two interior polygonal pads are configured such that a line running through and intersecting the angle at least one vertex of each of the two interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.
2. The semiconductor device of claim 1 , wherein the two internal polygonal pads are quadrilaterals and the line runs through two vertices of each of the interior polygonal pads.
3. The semiconductor device of claim 2 , wherein the line running through the two vertices of each of the two interior polygonal pads is a centerline of the rectangular boundary of the package structure.
4. The semiconductor device of claim 1 wherein the interior polygonal pads have side dimensions of 0.15 mm-0.25 mm.
5. The semiconductor device of claim 1 wherein the pitch of the interior polygonal pads is approximately 0.4 mm.
6. A semiconductor device comprising:
a semiconductor chip having conductive pads;
a package structure defining a rectangular boundary and having a bottom surface and comprising;
only two interior polygonal pads exposed at the bottom surface of the package structure, each of the two interior polygonal pads being physically and electrically separated from each other at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure; and
only six edge polygonal pads exposed at the bottom surface of the package structure, each of the six edge polygonal pads being located at an edge of the rectangular boundary, the edge polygonal pads including one edge polygonal pad in the vicinity of each corner of the rectangular boundary;
wherein each of the two interior polygonal pads has a first side that is parallel to a facing side of the edge polygonal pad that is nearest to the first side and a second side that is parallel to a facing side of the edge polygonal pad that is nearest to the second side, wherein the first side and the second side of each of the interior polygonal pads are not parallel to the rectangular boundary of the package structure; and
wherein the two interior polygonal pads are configured such that a line running through and intersecting the angle at least one vertex of each of the two interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure;
wherein each of the two interior polygonal pads and the edge polygonal pads is electrically connected to a different one of the conductive pads of the semiconductor chip.
7. The semiconductor device of claim 6 , wherein the two internal polygonal pads are quadrilaterals and the line runs through two vertices of each of the interior polygonal pads.
8. The semiconductor device of claim 7 , wherein the line running through the vertices of each of the interior polygonal pads is a centerline of the rectangular boundary of the package structure.
9. The semiconductor device of claim 6 wherein the interior polygonal pads have side dimensions of 0.15 mm-0.25 mm.
10. The semiconductor device of claim 6 wherein the pitch of the interior polygonal pads is approximately 0.4 mm.