IP Library Granted Patent US 9,953,722
Granted Patent B2
US 9,953,722 · App. 14/991,681 · Granted Apr 24, 2018

Methods of system optimization by over-sampling read

Inventors: David J. Pignatelli (Saratoga, CA); June Lee (Sunnyvale, CA); Fan Zhang (Fremont, CA)
Assignee: SK Hynix Inc.
G11C29/00G11C29/4401G11C29/52G11C29/76G11C2029/0411
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Quick Facts
Patent No.
US 9,953,722
App. No.
14/991,681
Granted
Apr 24, 2018
Kind
B2
Abstract

A method of controller optimization utilizing over-sampling read (OSR) in a memory device includes performing a first internal read at a predetermined threshold level and transferring the first internal read measurement to the controller, performing a second internal read in a range that is between the predetermined threshold level plus a first predetermined value and the predetermined threshold level minus a second predetermined value, and determining whether a cell level falls in the range and transferring the second internal read measurement to the controller.

Claims (36)

1. A method of controller optimization utilizing over-sampling read (OSR) in a memory device, comprising:

performing a first internal read at a predetermined threshold level and transferring the first internal read measurement to the controller;

performing a second internal read in a range that is between the predetermined threshold level plus a first predetermined value and the predetermined threshold level minus a second predetermined value;

measuring whether a cell level falls in the range and transferring second internal read measurement using the range to the controller, wherein the second internal read measurement is 0 when the cell level falls in the range, and the second internal read measurement is 1 when the cell level does not fall in the range;

generating an erasure count in accordance with the second internal read measurement;

estimating a number of errors in accordance with a percentage of errors calculated based on at least the erasure count, without decoding the first internal read measurement or second internal read measurement; and

optimizing a read threshold in accordance with at least the number of errors.

2. The method of claim 1 , wherein the memory device has a page length of N, such that transferring the first internal read measurement to the controller and transferring the second internal read measurement to the controller transfers 2*N bits to the controller.

3. The method of claim 1 , further comprising performing a read-reclaim by:

determining a number of erasures within the range; and

determining a percent of an error correcting capability based on the number of erasures and a code length.

4. The method of claim 3 , wherein the first internal read is performed in binary-symmetric channel.

5. The method of claim 3 , wherein the second internal read is performed in binary erasure channel.

6. The method of claim 1 , further comprising performing a read threshold optimization by:

determining whether the pre-determined threshold level provides a minimum number of erasures.

7. The method of claim 4 , further comprising updating the pre-determined threshold level when it is determined that the pre-determined threshold level does not provide the minimum number of erasures.

8. The method of claim 1 , further comprising generating an LLR with two or less OSR reads.

9. The method of claim 1 , wherein the first predetermined value and the second predetermined value are equal.

10. A system for controller optimization utilizing over-sampling read (OSR), comprising:

a NAND memory device including a controller, the NAND memory device is configured to:

perform a first internal read at a predetermined threshold level and transferring the first internal read measurement to the controller;

perform a second internal read in a range that is between the predetermined threshold plus a first predetermined value and the predetermined threshold minus a second predetermined value;

measure whether a cell level falls in the range and transfer second internal read measurement using the range to the controller, wherein the second internal read measurement is 0 when the cell level falls in the range, and the second internal read measurement is 1 when the cell level does not fall in the range;

generate an erasure count in accordance with the second internal read measurement;

estimate a number of errors in accordance with a percentage of errors calculated based on at least the erasure count, without decoding the first internal read measurement or second internal read measurement; and

optimize a read threshold in accordance with at least the number of errors.

11. The system of claim 10 , wherein the memory device has a page length of N, such that transferring the first internal read measurement to the controller and transferring the second internal read measurement to the controller transfers 2*N bits to the controller.

12. The system of claim 10 , wherein the device is further suitable for:

determining a number of erasures within the range; and

determining a percent of an error correcting capability based on the number of erasures and a code length to perform a read-reclaim.

13. The system of claim 12 , wherein the first internal read is performed in binary-symmetric channel.

14. The system of claim 12 , wherein the second internal read is performed in binary erasure channel.

15. The system of claim 10 , wherein the device is further suitable for determining whether the pre-determined threshold level provides a minimum number of erasures to perform a read threshold optimization.

16. The system of claim 15 , wherein the device is further suitable for updating the pre-determined threshold level when it is determined that the pre-determined threshold level does not provide the minimum number of erasures.

17. The system of claim 10 , wherein the device is suitable for generating an LLR with two or less OSR reads.

18. The system of claim 10 , wherein the first predetermined value and the second predetermined value are equal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 044899/0443 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: PIGNATELLI, DAVID J; LEE, JUNE; ZHANG, FAN
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 037717/0036 →
Continuity (2)
Provisional Application 62101308 · Jan 8, 2015
Related Publication 20160202934A1 · Jul 14, 2016