Nonvolatile memory devices and methods of programming and reading nonvolatile memory devices
In a method of programming a nonvolatile memory device, a program operation is performed on a selected memory cell coupled to a selected word line in response to a program command, a negative bias voltage is applied to the selected word line, a verification pass voltage is applied to an unselected word line after the negative bias voltage is applied to the selected word line, and a first program verification voltage, which is higher than the negative bias voltage and lower than a ground voltage, is applied to the selected word line.
1. A method of programming a nonvolatile memory device, the method comprising:
performing a program operation on a selected memory cell coupled to a selected word line in response to a program command;
applying a negative bias voltage to the selected word line;
applying a verification pass voltage to an unselected word line after the negative bias voltage is applied to the selected word line;
applying a first program verification voltage, which is higher than the negative bias voltage and lower than a ground voltage, to the selected word line; and
applying a second program verification voltage, which has a positive voltage level, to the selected word line after the first program verification voltage is applied to the selected word line.
2. The method of claim 1 , wherein the first program verification voltage is applied to the selected word line at a same time as the verification pass voltage is applied to the unselected word line.
3. The method of claim 1 , wherein the first program verification voltage is applied to the selected word line after a delay time from a time at which the verification pass voltage is applied to the unselected word line.
4. The method of claim 3 , wherein the delay time is adjusted based on a coupling capacitance between the selected word line and the unselected word line.
5. The method of claim 1 , wherein a magnitude of the negative bias voltage is determined based on a coupling capacitance between the selected word line and the unselected word line.
6. The method of claim 1 , wherein the negative bias voltage and the first program verification voltage are generated by a selected word line voltage generator, and
the verification pass voltage is generated by an unselected word line voltage generator.
7. The method of claim 1 , wherein the nonvolatile memory device comprises a three dimensional memory cell array.
8. A method of reading a nonvolatile memory device, the method comprising:
applying a negative bias voltage to a selected word line in response to a read command;
applying a read pass voltage to an unselected word line after the negative bias voltage is applied to the selected word line;
applying a first read voltage, which is higher than the negative bias voltage and lower than a ground voltage, to the selected word line; and
applying a second read voltage, which has a positive voltage level, to the selected word line after the first read voltage is applied to the selected word line.
9. The method of claim 8 , wherein the first read voltage is applied to the selected word line at a same time as the read pass voltage is applied to the unselected word line.
10. The method of claim 8 , wherein the first read voltage is applied to the selected word line after a delay time from a time at which the read pass voltage is applied to the unselected word line.
11. The method of claim 10 , wherein the delay time is adjusted based on a coupling capacitance between the selected word line and the unselected word line.
12. The method of claim 8 , wherein a magnitude of the negative bias voltage is determined based on a coupling capacitance between the selected word line and the unselected word line.
13. The method of claim 8 , wherein the negative bias voltage and the first read voltage are generated by a selected word line voltage generator, and
the read pass voltage is generated by an unselected word line voltage generator.
14. A method of performing a memory access operation to a nonvolatile memory device, the method comprising:
applying a negative bias voltage to a selected word line in response to a command;
applying an operation pass voltage to an unselected word line after the negative bias voltage is applied to the selected word line;
applying a first operation voltage, which is higher than the negative bias voltage and lower than a ground voltage, to the selected word line; and
wherein the first operation voltage is applied to the selected word line after a delay time from a time at which the operation pass voltage is applied to the unselected word line.
15. The method of claim 14 , wherein the memory access operation comprises a program operation, the negative bias voltage is applied after the program operation, the operation pass voltage comprises a verification pass voltage, and the first operation voltage comprises a first program verification voltage.
16. The method of claim 14 , wherein the memory access operation comprises a read operation, the operation pass voltage comprises a read pass voltage, and the first operation voltage comprises a first read voltage.