Semiconductor structure, electrode structure and method of forming the same
A semiconductor structure includes an N th metal layer, a diffusion barrier layer over the N th metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1) th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.
1. A semiconductor structure, comprising:
an N th metal layer;
a diffusion barrier layer over the N th metal layer;
a first deposition of electrode material over the diffusion barrier layer;
a second deposition of electrode material over the first deposition of electrode material;
a magnetic tunneling junction (MTJ) layer over the second deposition of electrode material;
a top electrode over the MTJ layer; and
an (N+1) th metal layer over the top electrode;
wherein the diffusion barrier layer and the first deposition of electrode material are laterally in contact with a dielectric layer, the first deposition of electrode material spacing the diffusion barrier layer and the second deposition of electrode material apart, and N is an integer greater than or equal to 1;
wherein a top surface of the diffusion barrier layer is uneven and a center region of the top surface is higher than an outer region of the top surface.
2. The semiconductor structure of claim 1 , wherein the first deposition of electrode material and a portion of the diffusion barrier layer form a tapered structure tapering toward the N th metal layer.
3. The semiconductor structure of claim 1 , wherein the diffusion barrier layer includes metal nitride materials.
4. The semiconductor structure of claim 3 , wherein the diffusion barrier layer includes tantalum nitride (TaN).
5. The semiconductor structure of claim 1 , wherein the first deposition of electrode material includes titanium nitride (TiN).
6. The semiconductor structure of claim 1 , wherein the dielectric layer includes a silicon carbide (SiC) layer.
7. The semiconductor structure of claim 1 , wherein the dielectric layer includes a silicon-rich oxide (SRO) layer.
8. The semiconductor structure of claim 1 , wherein the second deposition of electrode material includes TiN.
9. The semiconductor structure of claim 1 , wherein the semiconductor structure is a magnetic random access memory (MRAM) cell.
10. A semiconductor structure, comprising:
an N th metal layer;
a dielectric layer over the N th metal layer;
a diffusion barrier layer disposed in the dielectric layer, wherein the diffusion barrier layer is over and coupled to the N th metal layer;
a bottom electrode over the diffusion barrier layer;
a magnetic tunneling junction (MTJ) layer over the bottom electrode;
a top electrode over the MTJ layer; and
an (N+1) th metal layer over the top electrode;
wherein a top surface of the diffusion barrier layer is lower than a top surface of the dielectric layer, and N is an integer greater than or equal to 1;
wherein the top surface of the diffusion barrier layer is uneven and a center region of the top surface is higher than an outer region of the top surface.
11. The semiconductor structure of claim 10 , wherein the dielectric layer includes a silicon carbide (SiC) layer.
12. The semiconductor structure of claim 11 , wherein the dielectric layer further includes a silicon-rich oxide (SRO) layer over the SiC layer.
13. The semiconductor structure of claim 10 , wherein the bottom electrode includes titanium nitride (TiN).
14. The semiconductor structure of claim 10 , wherein the diffusion barrier layer includes metal nitride materials.
15. The semiconductor structure of claim 14 , wherein the diffusion barrier layer includes tantalum nitride (TaN).
16. The semiconductor structure of claim 10 , wherein the top surface of the diffusion barrier layer is lower than the top surface of the dielectric layer by about 100 angstroms to about 300 angstroms.
17. A semiconductor structure, comprising:
an N th metal layer;
a dielectric layer over the N th metal layer;
a diffusion barrier layer disposed in the dielectric layer, wherein the diffusion barrier layer is over and coupled to the N th metal layer;
a protection layer over the dielectric layer;
a bottom electrode over the diffusion barrier layer;
a magnetic tunneling junction (MTJ) layer over the bottom electrode;
a top electrode over the MTJ layer; and
an (N+1) th metal layer over the top electrode;
wherein a lower portion of the bottom electrode is disposed in the dielectric layer, and the MTJ layer and an upper portion of the bottom electrode is disposed in the protection layer; and
the diffusion barrier layer and the lower portion of the bottom electrode are laterally in contact with the dielectric layer, and N is an integer greater than or equal to 1;
wherein a top surface of the diffusion barrier layer is uneven and a center region of the top surface is higher than an outer region of the top surface.
18. The semiconductor structure of claim 17 , wherein the top surface of the diffusion barrier layer is lower than a top surface of the dielectric layer by about 100 angstroms to about 300 angstroms.