FinFET with source/drain structure

1. A semiconductor device, comprising:

a substrate including a first fin element, a second fin element, and a third fin element;

a first source/drain epitaxial feature disposed over the first and second fin elements, wherein a first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point;

a second source/drain epitaxial feature disposed over the third fin element,

wherein a first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element, and

wherein a second sidewall of the second source/drain epitaxial feature interfaces a second third-fin spacer disposed along a second sidewall of the third fin element;

wherein the merge point has a first height less than a second height of the first third-fin spacer.

2. The semiconductor device of claim 1 , further comprising:

a shallow trench isolation (STI) feature disposed between the first and second fin elements;

an air-gap interposing the first source/drain epitaxial feature and the STI feature, wherein the air-gap is defined by at least a first sidewall of the first portion of the first source/drain feature, a second sidewall of the second portion of the first source/drain epitaxial feature, and a top surface of the STI feature, wherein the merge point is defined by the air-gap.

3. The semiconductor device of claim 1 , wherein a third sidewall of the first source/drain epitaxial feature interfaces a first-fin spacer disposed along a second first-fin sidewall of the first fin element, and

wherein a fourth sidewall of the first source/drain epitaxial feature interfaces a second-fin spacer disposed along a second second-fin sidewall of the second fin element.

4. The semiconductor device of claim 1 , further comprising:

a third source/drain epitaxial feature disposed over a fourth fin element disposed over the substrate,

wherein the fourth fin element is adjacent to the third fin element,

wherein a first distance between the first and second fin elements is less than a second distance between the third and fourth fin elements,

wherein a first sidewall of the third source/drain epitaxial feature interfaces a first fourth-fin spacer disposed along a first sidewall of the fourth fin element, and

wherein a second sidewall of the third source/drain epitaxial feature interfaces a second fourth-fin spacer disposed along a second sidewall of the fourth fin element.

5. The semiconductor device of claim 1 , wherein each of the first and second third-fin spacers further includes:

a first spacer layer disposed over the substrate; and

a second spacer layer disposed over the first spacer layer.

6. The semiconductor device of claim 1 , further comprising:

a third spacer disposed between a fourth fin element and a fifth fin element disposed over the substrate,

wherein a first sidewall of the third spacer interfaces a first fourth-fin sidewall of the fourth fin element, and

wherein a second sidewall of the third spacer interfaces a first fifth-fin sidewall of the fifth fin element;

a fourth spacer disposed along a second fourth-fin sidewall of the fourth fin element; and

a fifth spacer disposed along a second fifth-fin sidewall of the fifth fin element;

wherein a first height of the third spacer is greater than a second height of the fourth spacer.

7. The semiconductor device of claim 6 , wherein each of the third, fourth, and fifth spacers includes:

a first spacer layer disposed over the substrate; and

a second spacer layer disposed over the first spacer layer.

8. The semiconductor device of claim 6 , wherein the first height is at least about 30% greater than the second height.

9. A semiconductor device, comprising:

a substrate including a first fin element, a second fin element adjacent to the first fin element, and a shallow trench isolation (STI) feature disposed between the first and second fin elements;

a first source/drain epitaxial feature disposed on the first and second fin elements,

wherein a first sidewall of the first source/drain epitaxial feature interfaces a first spacer disposed along a first first-fin sidewall of the first fin element facing away from the second fin element, and

wherein a second sidewall of the first source/drain epitaxial feature interfaces a second spacer disposed along a first second-fin sidewall of the second fin element facing away from the first fin element;

an air-gap interposing the first source/drain epitaxial feature and the STI feature,

wherein the air-gap has a first height less than a second height of the first spacer, and is at least partially defined by a third sidewall and a fourth sidewall of the first source/drain epitaxial feature and a top surface of the STI feature.

10. The semiconductor device of claim 9 , wherein the first height is less than about 30% of the second height.

11. The semiconductor device of claim 9 , further comprising:

a third spacer disposed along a second first-fin sidewall of the first fin element facing toward the second fin element;

a fourth spacer disposed along a second second-fin sidewall of the second fin element facing toward the first fin element;

wherein a third height of the third spacer is less than the first height of the air-gap.

12. The semiconductor device of claim 9 , wherein a first material of the third and fourth spacers has a first dopant concentration, and

wherein a second material of the first and second spacers has a second dopant concentration greater than the first dopant concentration.

13. The semiconductor device of claim 9 , further comprising:

the difference between the second dopant concentration and the first dopant concentration is greater than about 10%.

14. The semiconductor device of claim 13 , further comprising:

a second source/drain epitaxial feature disposed on a third fin element disposed over the substrate, wherein the second source/drain epitaxial feature interfaces two third-fin spacers disposed along sidewalls of the third fin element; and

a third source/drain epitaxial feature disposed on a fourth fin element adjacent to the third fin element, wherein the third source/drain epitaxial feature interfaces two third-fin spacers disposed along sidewalls of the third fin element;

wherein a first distance between the first and second fin elements is less than a second distance between the third and fourth fin elements.

15. A semiconductor device, comprising:

a substrate including a first fin element, a second fin element adjacent to the first fin element, a third fin element;

a first source/drain epitaxial feature disposed over the first and second fin elements, wherein a first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point;

a second source/drain epitaxial feature disposed over the third fin element;

wherein a first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element, and

wherein the merge point has a first height less than a second height of the first third-fin spacer.

16. A semiconductor device of claim 15 , further comprising:

a shallow trench isolation (STI) feature disposed between the first and second fin elements;

an air-gap interposing the first source/drain epitaxial feature and the STI feature, wherein the air-gap is defined by at least a first sidewall of the first portion of the first source/drain feature, a second sidewall of the second portion of the first source/drain epitaxial feature, and a top surface of the STI feature, wherein the merge point is defined by the air-gap.

17. The semiconductor device of claim 15 , wherein a third sidewall of the first source/drain epitaxial feature interfaces a first-fin spacer disposed along a second first-fin sidewall of the first fin element, and

wherein a fourth sidewall of the first source/drain epitaxial feature interfaces a second-fin spacer disposed along a second second-fin sidewall of the second fin element.

18. The semiconductor device of claim 15 , further comprising:

a fourth fin element adjacent to the third fin element;

a third source/drain epitaxial feature disposed over the fourth fin element,

wherein a second sidewall of the third source/drain epitaxial feature interfaces a first fourth-fin spacer disposed along a first sidewall of the fourth fin element, and

wherein the first height of the merge point is less than a third height of the first fourth-fin spacer.

19. The semiconductor device of claim 18 ,

wherein a first distance between the first and second fin elements is less than a second distance between the third and fourth fin elements,

wherein a first sidewall of the third source/drain epitaxial feature interfaces the first fourth-fin spacer disposed, and

wherein a second sidewall of the third source/drain epitaxial feature interfaces a second fourth-fin spacer disposed along a second sidewall of the fourth fin element.

20. The semiconductor device of claim 18 , wherein each of the first third-fin spacer and the first fourth-fin spacer further includes:

a first spacer layer disposed over the substrate; and

a second spacer layer disposed over the first spacer layer.