Fast memory initialization
In an example, there is disclosed a memory controller, including: a data buffer to drive a determinate value to a data bus to communicatively couple to a memory; and a register clock driver to: receive a memory initialization command from a processor; and incrementally step through a plurality of initialization addresses, sequentially driving each initialization address to an address bus to communicatively couple to the memory. There is also disclosed a computing device comprising the memory controller, and a method of initializing memory comprising incrementally stepping through a plurality of initialization addresses and sequentially writing a determinate value to each address.
1. An apparatus, comprising:
a first memory bank comprising a first memory module;
a first data buffer coupled to the first memory bank;
a second memory bank comprising a second memory module;
a second data buffer coupled to the second memory bank; and
a memory driver comprising circuitry, the memory driver communicatively coupled to the first memory module and the second memory module, the memory driver to:
receive a memory initialization command from a processor;
responsive to the memory initialization command, scramble a plurality of addresses of the first memory module and the second memory module and incrementally step through the plurality of scrambled addresses, writing one or more determinate values to the plurality of scrambled addresses, wherein writing one or more determinate values to the plurality of scrambled addresses comprises simultaneously writing contents of the first data buffer to the first memory module of the first memory bank and writing contents of the second data buffer to the second memory module of the second memory bank; and
receive a hash key from the processor and use the hash key to generate the plurality of scrambled addresses responsive to the memory initialization command.
2. The apparatus of claim 1 , further comprising the processor, and wherein the memory driver is further to notify the processor of a status of the memory initialization command.
3. The apparatus of claim 2 , wherein notifying the processor comprises notifying the processor of success.
4. The apparatus of claim 2 , wherein notifying the processor comprises notifying the processor of failure.
5. The apparatus of claim 4 , wherein notifying the processor of failure comprises changing the polarity of a data bus.
6. The apparatus of claim 4 , wherein notifying the processor of failure comprises writing to a register.
7. The apparatus of claim 1 , wherein the one or more determinate values are all zeros.
8. The apparatus of claim 7 , wherein writing a zero comprises pulling a data input to ground.
9. The apparatus of claim 1 , wherein the memory driver is further to multiplex a processor data input with a determinate value of the one or more determinate values.
10. The apparatus of claim 1 , wherein the memory driver is further to multiplex a processor-supplied address with an address of the plurality of scrambled addresses.
11. A memory driver, comprising:
a first data buffer to couple to a first memory module of a first memory bank;
a second data buffer to couple to a second memory module of a second memory bank; and
a register clock driver to:
receive a memory initialization command from a processor;
responsive to the memory initialization command, scramble a plurality of addresses of the first memory module and the second memory module and incrementally step through the plurality of scrambled addresses, writing one or more determinate values to the plurality of scrambled addresses, wherein writing one or more determinate values to the plurality of scrambled addresses comprises simultaneously writing contents of the first data buffer to the first memory module of the first memory bank and writing contents of the second data buffer to the second memory module of the second memory bank; and
receive a hash key from the processor and use the hash key to generate the plurality of scrambled addresses responsive to the memory initialization command.
12. The memory driver of claim 11 , wherein the memory driver is further to notify the processor of a status of the memory initialization command.
13. The memory driver of claim 12 , wherein notifying the processor comprises notifying the processor of success.
14. The memory driver of claim 12 , wherein notifying the processor comprises notifying the processor of failure.
15. The memory driver of claim 12 , wherein notifying the processor of failure comprises writing to a register.
16. The memory driver of claim 11 , wherein the register clock driver further comprises an initialization output to communicatively couple to an initialization input of a data bus, and wherein the data bus is to drive the one or more determinate values to the data bus only as long as the initialization input is driven.
17. The memory driver of claim 11 , wherein the one or more determinate values are all zeros.
18. The memory driver of claim 11 , wherein the first data buffer further comprises a multiplexer to select between a processor-supplied data value and the one or more determinate values.
19. The memory driver of claim 11 , wherein the register clock driver further comprises a multiplexer to select between a processor-supplied address and the plurality of scrambled addresses.
20. A computer-implemented method of initializing a plurality of memory modules, comprising:
receiving a memory initialization command from a processor;
responsive to the memory initialization command, scrambling a plurality of addresses of a first memory module of a first memory bank and a second memory module of a second memory bank, incrementally stepping through the plurality of scrambled addresses, and writing one or more determinate values to the plurality of scrambled addresses, wherein writing one or more determinate values to the plurality of scrambled addresses comprises simultaneously writing contents of a first data buffer to the first memory module of the first memory bank and writing contents of a second data buffer to the second memory module of the second memory bank; and
receiving a hash key from the processor and using the hash key to generate the plurality of scrambled addresses responsive to the memory initialization command.
21. The computer-implemented method of claim 20 , further comprising notifying the processor of success or failure.
22. The apparatus of claim 1 , the memory driver to provide an address of the plurality of scrambled addresses to the first memory bank and the second memory bank during a parallel initialization of the first memory bank and the second memory bank performed responsive to the memory initialization command.
23. The apparatus of claim 1 , the memory driver further to latch a determinate value to the first data buffer coupled to the first memory bank and to the second data buffer coupled to the second memory bank responsive to the memory initialization command, the latched determinate value to be simultaneously written to the first memory module of the first memory bank and the second memory module of the second memory bank.
24. The apparatus of claim 1 , the memory driver further to receive an address range from the processor or to poll memory to determine the address range and responsive to the memory initialization command incrementally step through the address range to initialize the memory.