Polarization versatile radiator
A unit cell of an array antenna includes an integrated dilation and feed circuit and an associated radiator assembly. The integrated dilation and feed circuit includes an asymmetric dilation layer, an asymmetric combiner layer, a symmetric feed layer and a symmetric slot layer. Feed circuits on the feed layer are configured to couple radio frequency (RF) signals to/from a pair of orthogonally disposed slot elements symmetrically disposed on the slot layer of the integrated dilation-feed circuit. The slot layer couples signals to and from the radiator assembly. Such unit cell may be used to provide an array antenna including an active electronically scanned array (AESA) antenna.
1. An integrated dilation and feed circuit comprising:
an asymmetric a dilation layer comprising a pair of dilation circuit signal paths;
an asymmetric reactive combiner layer comprising a pair of reactive combiner circuits, said asymmetric reactive combiner circuit layer disposed over said asymmetric dilation layer such that said pair of reactive combiner circuits are coupled to respective ones of said pair of dilation circuit signal paths;
a symmetric feed layer having a plurality of feed circuits symmetrically disposed thereon, said symmetric feed layer disposed over said asymmetric asymmetric reactive combiner layer such that each of said symmetrically disposed plurality of feed circuits are coupled to one of said pair of asymmetric, reactive combiner circuits, wherein said symmetric feed layers is both physically and electrically symmetric; and
a symmetric slot layer having a like plurality of slots symmetrically disposed thereon, said symmetric slot layer disposed over said symmetric feed layer such that each of said plurality of feed circuits intersect a respective one of said plurality of slots, wherein said symmetric slot layer is both physically and electrically symmetric.
2. The integrated dilation and feed circuit of claim 1 further comprising:
a pair of substrates, each having first and second opposing surfaces;
a pair of ground planes disposed on corresponding first surfaces of said pair of substrates; and
wherein said asymmetric a dilation circuit layer is disposed on a second surface of one substrate opposite the ground plane.
3. The integrated dilation and feed circuit of claim 1 further comprising:
a pair of substrates, each having first and second opposing surfaces;
a pair of ground planes disposed on corresponding first surfaces of said pair of substrates; and
wherein said asymmetric reactive combiner layer is disposed on a second surface of one substrate opposite the ground plane.
4. The integrated dilation and feed circuit of claim 1 further comprising:
a pair of substrates, each having first and second opposing surfaces;
a pair of ground planes disposed on corresponding first surfaces of said pair of substrates; and
wherein said symmetric feed layer is disposed on a second surface of one substrate opposite the ground plane.
5. The integrated dilation and feed circuit of claim 1 wherein said slot layer is provided as a conductive layer having slots provided therein.
6. The integrated dilation and feed circuit of claim 1 wherein said symmetric slot layer is provided as a conductive layer having slots symmetrically provided therein.
7. The integrated dilation and feed circuit of claim 1 wherein each of said plurality of feed circuits symmetrically cross a respective one of said plurality of symmetric slots.
8. The integrated dilation and feed circuit of claim 2 further comprising a pair of radio frequency (RF) connectors disposed on one of said pair of ground planes with a first one of said pair of RF connectors and coupled to a first end of a first one of said pair of dilation circuit signal paths and a second one of said pair of RF connectors coupled to a first end of a second one of said pair of dilation circuit signal paths.
9. The integrated dilation and feed circuit of claim 1 further comprising:
a first pair of substrates, each having first and second opposing surfaces and a first pair of ground planes disposed on corresponding first surfaces of said first pair of substrates wherein said asymmetric a dilation circuit layer is disposed on a second surface of one substrate of said first pair of substrates opposite the ground plane;
a second pair of substrates disposed over said first pair of substrates, each of said second pair of substrates having first and second opposing surfaces and a second pair of ground planes disposed on corresponding first surfaces of said second pair of substrates, wherein said asymmetric reactive combiner layer is disposed on a second surface of one substrate of said second pair of substrates opposite the ground plane;
a third pair of substrates each having first and second opposing surfaces, said third pair of substrates disposed over said second pair of substrates such that a first surface of a first one of said third pair of substrates is disposed on one of the second pair of ground planes, and wherein said symmetric feed layer is disposed on a second surface of one substrate of said third pair of substrates; and
wherein said slot layer is provided as a conductive layer disposed over a surface of the second one of said third pair of substrates.
10. The integrated dilation and feed circuit of claim 1 further comprising a plurality of conductive vias provided in said second pair of substrates and said asymmetric reactive combiner layer, said conductive vias extending between the second pair of ground planes, said plurality of conductive vias disposed between signal paths of said pair of reactive combiner circuits.
11. The integrated dilation and feed circuit of claim 10 further comprising a plurality of conductive vias provided in said dilation layer and disposed throughout said dilation layer to suppress undesired electromagnetic fields in said dilation layer.
12. The integrated dilation and feed circuit of claim 1 wherein each of said plurality of feed circuits symmetrically cross a respective one of said plurality of symmetric slots.
13. A polarization diverse antenna comprising:
an integrated dilation and feed circuit comprising:
an asymmetric a dilation layer comprising a pair of dilation circuit signal paths;
an asymmetric reactive combiner layer comprising a pair of reactive combiner circuits, said asymmetric reactive combiner circuit layer disposed over said asymmetric dilation layer such that said pair of reactive combiner circuits are coupled to respective ones of said pair of dilation circuit signal paths;
a symmetric feed layer having a plurality of feed circuits symmetrically disposed thereon, said symmetric feed layer disposed over said asymmetric asymmetric reactive combiner layer such that each of said symmetrically disposed plurality of feed circuits are coupled to one of said pair of asymmetric, reactive combiner circuits; and
a symmetric slot layer having a like plurality of slots symmetrically disposed thereon, said symmetric slot layer disposed over said symmetric feed layer such that each of said plurality of feed circuits intersect a respective one of said plurality of slots; and
a radiator assembly comprising at least one radiator, said radiator assembly disposed over said integrated dilation and feed circuit such that the slots in said symmetric slot layer are disposed to coupled RF signals between at least one radiator and said plurality of symmetric feed circuits.
14. The antenna of claim 12 wherein said plurality of feed circuits are disposed on said substrate such that when a first surface of the slot layer is disposed over a first surface of the feed layer, said plurality of feed circuits orthogonally cross respective ones of said plurality of slot apertures such that RF energy may be coupled between the slots in said slot layer and the feed circuits on said feed layer.
15. The antenna of claim 12 wherein said plurality of feed circuits correspond to four feed circuits and said plurality of slots correspond to four diagonal slots and wherein respective ones of said four feed circuits cross respective ones of said four slots.
16. The antenna of claim 12 wherein radiator assembly comprises:
a conductive frame having walls which define a cavity; and
a radiator disposed in the cavity.
17. The antenna of claim 13 wherein said radiator is provided as a patch antenna element.
18. The antenna of claim 16 wherein said patch antenna is provided as a symmetrical stacked-patch antenna comprising inner and outer conductors spaced apart by a foam spacer and dielectric substrates.
19. The antenna of claim 18 wherein said combiner, feed and slot layers are disposed relative to said patch antenna element so as to generate a pair of orthogonal electric field vectors with respect to said patch element.
20. The antenna of claim 13 further comprising:
a first plurality of conductive vias provided in the perimeter of each of said asymmetric dilation layer, asymmetric reactive combiner layer, symmetric feed layer and symmetric slot layer so as to form an RF cage in the integrated dilation and feed circuit;
a second plurality of conductive vias provided in said dilation layer and disposed throughout said dilation layer to suppress undesired electromagnetic fields in said dilation layer wherein said second plurality of conductive vias do not penetrate to said combiner circuit layer, said feed circuit layer or said slot layer; and
a third plurality of conductive vias provided in said asymmetric reactive combiner layer between signal path regions of said pair of asymmetric reactive combiner circuits.
21. An active electronically scanned array (AESA) comprising:
an egg-crate frame having a plurality of electrically conductive walls which define a plurality of cavities; and
a plurality of polarization diverse radiators, each of said polarization diverse radiators disposed within one of the plurality of cavities in said egg-crate frame, each of said plurality of polarization diverse radiators comprising:
an inner antenna element provided from one or more substrates having a conductor disposed thereon with each of the one or more inner antenna element substrates having dimensions such that said antenna element fits inside the cavity;
an outer antenna element provided from one or more substrates having a conductor disposed thereon, said one or more outer antenna element substrates having substantially the same dimensions as the one or more inner antenna element substrates; and
a dielectric spacer disposed between the inner and outer antenna elements, said dielectric spacer having substantially the same dimensions as the one or more inner and outer antenna element substrates; and
an integrated dilation and feed circuit disposed over and coupled to said plurality of polarization diverse radiators, said integrated dilation and feed circuit comprising:
an asymmetric a dilation layer comprising a pair of dilation circuit signal paths;
an asymmetric reactive combiner layer comprising a pair of reactive combiner circuits, said asymmetric reactive combiner circuit layer disposed over said asymmetric dilation layer such that said pair of reactive combiner circuits are coupled to respective ones of said pair of dilation circuit signal paths;
a symmetric feed layer having a plurality of feed circuits symmetrically disposed thereon, said symmetric feed layer disposed over said asymmetric asymmetric reactive combiner layer such that each of said symmetrically disposed plurality of feed circuits are coupled to one of said pair of asymmetric, reactive combiner circuits; and
a symmetric slot layer having a like plurality of slots symmetrically disposed thereon, said symmetric slot layer disposed over said symmetric feed layer such that each of said plurality of feed circuits intersect a respective one of said plurality of slots such that the slots in said symmetric slot layer are disposed to coupled RF signals between plurality of polarization diverse radiators and said symmetric feed layer.
22. The active electronically scanned array (AESA) of claim 21 wherein each of the inner antenna elements and the outer antenna elements are disposed to provide symmetrical stacked patch antenna elements with each of said stacked patch antenna elements symmetrically disposed within a respective one of the plurality of cavities.
23. The active electronically scanned array (AESA) of claim 22 wherein the slots in the symmetric slot layer correspond to slotted aperture couplers, with each of the slotted aperture couplers having an orientation that provides full power transfer for orthogonal circular polarizations and horizontal and vertical polarizations.
24. The active electronically scanned array (AESA) of claim 23 wherein the slotted aperture couplers are provided having a 45 degree orientation such that the slotted aperture couplers provide full power transfer for electric fields having at least one of: orthogonal circular polarizations; a horizontal polarization; and a vertical polarization.