METHOD AND APPARATUS FOR A HIGH YIELD CONTACT INTEGRATION SCHEME
A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.
1 . A device comprising:
a wafer;
one or more semiconductor devices including source/drain regions on the wafer;
a dielectric material between the one or more semiconductor devices;
one or more contact areas, through the dielectric material, having a tight tip-to-tip contact spacing,
wherein the contact areas are formed by:
forming one or more trench patterning layers on a planarized surface of the wafer;
forming one or more trenches in the one or more trench patterning layers;
forming a block mask at one or more points along the one or more trenches;
extending the one or more trenches down to a substrate level of the wafer; and
removing the block mask from the one or more points.
2 . The device according to claim 1 , wherein the critical dimension of the block mask is 10 nanometers (nm) to 150 nm.
3 . The device according to claim 1 , wherein the block mask comprises photoresist, silicon nitride (SiN), titanium nitride (TiN), or a combination thereof.
4 . The device according to claim 1 , wherein the one or more trenches are formed with a double patterning process.
5 . The device according to claim 1 , wherein the one or more points are associated with a tight tip-to-tip contact spacing parameter.
6 . The device according to claim 1 , wherein the one or more trenches extend down to one or more contact areas of one or more semiconductor devices formed on the wafer.
7 . The device according to claim 1 , wherein a first trench patterning layer of a dielectric material is formed to a thickness greater than 10 nanometers (nm).
8 . The device according to claim 7 , wherein a second trench patterning layer of silicon nitride (SiN), silicon dioxide (SiO 2 ), titanium (Ti) or silicon carbide (SiC) is formed to a thickness greater than 10 nm.
9 . The device according to claim 8 , wherein the one or more semiconductor devices are beneath the first trench patterning layer and second trench patterning layer.
10 . The device according to claim 1 , wherein a critical dimension of the block mask corresponds to a tip-to-tip contact spacing.
11 . The device according to claim 1 , further comprising shallow trench isolation (STI) regions.
12 . The device according to claim 1 , wherein one or more large contact-to-contact spacings are defined when the one or more first and second trenches are formed.
13 . A device comprising:
a wafer;
one or more semiconductor devices including source/drain regions on the wafer;
a dielectric material between the one or more semiconductor devices;
one or more contact areas, through the dielectric material, having a tight tip-to-tip contact spacing,
wherein the contact areas are formed by:
forming one or more trench patterning layers on a planarized surface of the wafer;
forming one or more trenches in the one or more trench patterning layers;
forming a block mask at one or more points along the one or more trenches;
extending the one or more trenches down to one or ore source/drain regions of the one or more semiconductor devices formed on the wafer; and
removing the block mask from the one or more points,
wherein the tip-to-tip contact spacing corresponds to a critical dimension (CD) of the block mask, and
a CD of the block mask is 10 nanometers (nm) to 150 nm.
14 . The device of claim 13 , wherein the block mask comprises photoresist, SiN, titanium nitride (TiN), or a combination thereof.
15 . The device according to claim 13 , wherein the one or more trenches are formed with a double patterning process.
16 . The device according to claim 13 , wherein the one or more points are associated with a tight tip-to-tip contact spacing parameter.
17 . The device according to claim 13 , wherein a first trench patterning layer comprises a dielectric material and is formed to a thickness greater than 10 nanometers (nm).
18 . The device according to claim 17 , wherein a second trench patterning layer comprises silicon nitride (SiN), silicon dioxide (SiO 2 ), titanium (Ti) or silicon carbide (SiC) and is formed to a thickness greater than 10 nm.
19 . The device according to claim 13 , further comprising shallow trench isolation (STI) regions.
20 . A device comprising:
a wafer;
one or more semiconductor devices including source/drain regions on the wafer;
shallow trench isolation (STI) regions;
a dielectric material between the one or more semiconductor devices;
one or more contact areas, through the dielectric material, having a tight tip-to-tip contact spacing,
wherein the contact areas are formed by:
forming a first and second trench patterning layers on a planarized surface of the wafer, wherein the first trench patterning layer comprises a dielectric material having a thickness of greater than 10 nanometers (nm), and the second trench patterning layer comprises silicon nitride (SiN), silicon dioxide (SiO 2 ), titanium (Ti) or silicon carbide (SiC) and having a thickness greater than 10 nm;
forming one or more trenches in the one or more trench patterning layers;
forming a block mask at one or more points along the one or more trenches;
extending the one or more trenches down to one or ore source/drain regions of the one or more semiconductor devices formed on the wafer; and
removing the block mask from the one or more points,
wherein the tip-to-tip contact spacing corresponds to a critical dimension (CD) of the block mask, and
a CD of the block mask is 10 nanometers (nm) to 150 nm.