Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark
A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark trench. An alignment/overlay mark includes at least one insulating material positioned within the alignment/overlay mark trench. The alignment/overlay mark is devoid of any of the fin structures.
1. A device, comprising:
a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark trench; and
an alignment/overlay mark comprising at least one insulating material positioned within said alignment/overlay mark trench, wherein said alignment/overlay mark is devoid of any of said fin structures.
2. The device of claim 1 , further comprising a plurality of FinFET semiconductor devices formed in and above said semiconductor substrate.
3. The device of claim 1 , wherein an upper surface of said alignment/overlay mark trench is substantially coplanar with an upper surface of said semiconductor substrate.
4. The device of claim 1 , wherein sidewalls of said fin structures partially define a perimeter of said alignment/overlay mark.
5. The device of claim 1 , wherein at least some of said plurality of fin structures have a U-shaped configuration when viewed from above.
6. The device of claim 5 , wherein a bottom of said U-shaped configuration at least partially defines a perimeter of said alignment/overlay mark trench.
7. The device of claim 1 , wherein said alignment/overlay mark, when viewed from above, has one of a cross configuration, a chevron configuration, a grating pattern configuration, a number configuration, or a letter configuration.
8. A device, comprising:
a plurality of spaced-apart fin structures formed in a semiconductor substrate, wherein sidewalls of said fin structures at least partially define a perimeter of an alignment/overlay mark trench;
an alignment/overlay mark comprising at least one insulating material positioned within said alignment/overlay mark trench, wherein said alignment/overlay mark is devoid of any of said fin structures; and
a plurality of FinFET semiconductor devices formed in and above said semiconductor substrate.
9. The device of claim 8 , wherein an upper surface of said alignment/overlay mark trench is substantially coplanar with an upper surface of said semiconductor substrate.
10. The device of claim 8 , wherein at least some of said plurality of fin structures have a U-shaped configuration when viewed from above.
11. The device of claim 10 , wherein a bottom of said U-shaped configuration at least partially defines a perimeter of said alignment/overlay mark trench.
12. The device of claim 8 , wherein said alignment/overlay mark, when viewed from above, has one of a cross configuration, a chevron configuration, a grating pattern configuration, a number configuration, or a letter configuration.
13. A device, comprising:
a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark trench, wherein an upper surface of said alignment/overlay mark trench is substantially coplanar with an upper surface of said semiconductor substrate;
an alignment/overlay mark comprising at least one insulating material positioned within said alignment/overlay mark trench, wherein said alignment/overlay mark is devoid of any of said fin structures; and
a plurality of FinFET semiconductor devices formed in and above said semiconductor substrate.
14. The device of claim 13 , wherein sidewalls of said fin structures partially define a perimeter of said alignment/overlay mark.
15. The device of claim 13 , wherein at least some of said plurality of fin structures have a U-shaped configuration when viewed from above.
16. The device of claim 15 , wherein a bottom of said U-shaped configuration at least partially defines a perimeter of said alignment/overlay mark trench.
17. The device of claim 13 , wherein said alignment/overlay mark, when viewed from above, has one of a cross configuration, a chevron configuration, a grating pattern configuration, a number configuration, or a letter configuration.