IP Library › Granted Patent US 10,101,927
Granted Patent B2
US 10,101,927 · App. 15/002,083 · Granted Oct 16, 2018

Data storage device and operating method thereof

Inventors: Soo Nyun Kim (Gyeonggi-do, KR); Jin Woong Kim (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
G06F3/0619G06F3/065G06F3/0608G06F3/0665G06F3/0679G06F3/0688G06F12/0246G06F2212/7201G06F2212/7209
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,101,927
App. No.
15/002,083
Granted
Oct 16, 2018
Kind
B2
Abstract

A data storage device includes a nonvolatile memory device, and a controller configured to construct logical address sets each including a start logical address and valid address flags corresponding to the start logical address, from logical addresses provided from a host device, generate an address mapping table by mapping each of the logical address sets to a physical address of the nonvolatile memory device, and perform a request from the host device, by referring to the address mapping table.

Claims (24)

1. A data storage device comprising:

a nonvolatile memory device; and

a controller suitable for constructing a plurality of logical address set based on all logical addresses provided from a host device, wherein each of the plurality of logical address sets includes a start logical address of one or more logical addresses included in a corresponding logical address set and one or more valid address flags corresponding to each of the one or more logical addresses and for generating an address mapping table by mapping each of the plurality of logical address sets to a physical address of the nonvolatile memory device,

wherein the one or more valid address flags indicates whether the corresponding each of the one or more logical addresses is valid or not,

wherein a valid logical address includes a logical address existing in the address mapping table or a logical address mapped to the physical address, and

wherein the controller determines that a logical address corresponding to a valid address flag in a set state is the valid logical address and a logical address corresponding to a valid address flag in a reset state is an invalid logical address.

2. The data storage device according to claim 1 , wherein the controller increases start logical addresses of the logical address sets from one to another, by the number of the valid address flags.

3. The data storage device according to claim 1 , wherein the controller uses at least one of an address of a memory block of the nonvolatile memory device, an address of a page identifying the memory block and an offset identifying the page, as the physical address.

4. A data storage device comprising:

a nonvolatile memory device; and

a controller suitable:

for constructing a plurality of logical address sets based on all logical addresses, wherein each of the plurality of logical address sets includes a start logical address of one or more logical addresses included in a corresponding logical address set and one or more valid address flags corresponding to each of the one or more logical addresses,

wherein the one or more valid address flags indicates whether the corresponding each of the one or more logical addresses is valid or not, and

wherein a valid logical address includes a logical address mapped to a physical address of the nonvolatile memory device.

5. The data storage device according to claim 4 , wherein start logical addresses of first and second logical address sets are apart in addresses by the number of the valid address flags.

6. A method for operating a data storage device a nonvolatile memory device, comprising:

constructing a plurality of logical address sets based on all logical addresses provided from a host device, wherein each of the plurality of logical address sets includes a start logical address of one or more logical addresses included in a corresponding logical address set and one or more valid address flags corresponding to each of the one or more logical addresses;

generating an address mapping table by mapping each of the plurality of logical address sets to a physical address of the nonvolatile memory device; and

performing a request from the host device, by referring to the address mapping table,

wherein the one or more valid address flags indicates whether the corresponding each of the one or more logical addresses is valid or not,

wherein a valid logical address includes a logical address existing in the address mapping table or a logical address mapped to the physical address, and

wherein the performing of the request includes determining that a logical address corresponding to a valid address flag in a set state is the valid logical address and a logical address corresponding to a valid address flag in a reset state is an invalid logical address.

7. The method according to claim 6 , wherein start logical addresses of the logical address sets are increased from one to another by the number of the valid address flags.

8. The method according to claim 6 , wherein the physical address includes at least one of an address of a memory block of the nonvolatile memory device, an address of a page identifying the memory block and an offset identifying the page.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2016
From: KIM, SOO NYUN; KIM, JIN WOONG
To: SK HYNIX INC.
Reel/Frame 037537/0809 →
Priority Claims (1)
KR 10-2015-0155567 · Nov 6, 2015 · national
Continuity (1)
Related Publication 20170131925A1 · May 11, 2017
Cited By (1)
US 12,346,250