System and method for low latency communication
View Patent ↗A system and method for low latency and higher bandwidth communication between a central processing unit (CPU) and an accelerator is disclosed. When the CPU updates a copy of data stored at a shared memory, the CPU also sends an “invalidate” command to a cache coherent interconnect (CCI). The CCI forwards the invalidate command to a dedicated cache register (DCR). The DCR marks its copy of the data as “out-of-date” and requests an up-to-date copy of the data from the CCI. The CCI then retrieves up-to-date data for the DCR. When the DCR receives the up-to-date data from the CCI, the DCR replaces the out-of-date data with the up-to-date data, and marks the up-to-date data with the status of “valid.” The DCR can then provide data to an accelerator with a status of “out-of-date” or “valid.”
1. A method comprising:
receiving, by a dedicated cache register (DCR), an indication from a cache coherent interconnect (CCI) that a copy of shared data at the DCR is out-of-date;
marking, by the DCR, the shared data copy at the DCR as out-of-date;
sending, by the DCR, a request for an up-to-date copy of the shared data;
receiving, by the DCR, the up-to-date copy of the shared data;
replacing, by the DCR, the out-of-date copy of the shared data at the DCR with the up-to-date copy of the shared data at the DCR;
marking, by the DCR, the replacement up-to-date shared data copy at the DCR as valid; and
providing, by the DCR, the shared data to an accelerator.
2. The method of claim 1 , wherein the shared data includes one or more data entries, wherein each data entry has a corresponding data value and data state.
3. The method of claim 2 , wherein the data state can be selected from the group consisting of valid, invalid, and out-of-date, wherein only data entries with the data state of out-of date or valid are provided to the accelerator.
4. The method of claim 1 further comprising:
informing the accelerator that the shared data copy is valid after the replacement up-to-date shared data copy is marked valid.
5. The method of claim 4 further comprising:
informing the accelerator that the shared data copy is out-of-date after marking the shared data copy as out-of-date.
6. The method of claim 5 further comprising:
providing the out-of-date copy of the shared data to the accelerator prior to replacing the out-of-date copy of the shared data with the up-to-date copy of the shared data.
7. The method of claim 1 , wherein the indication that the copy of shared data is out-of-date is originated by a central processing unit (CPU).
8. The method of claim 1 , wherein the accelerator specifies a policy about receiving out-of-date shared data.
9. A system comprising:
a central processing unit (CPU) configured to generate an indication that a copy of shared data is out-of-date;
a cache coherent interconnect (CCI) configured to receive the indication;
an accelerator; and
a dedicated cache register (DCR), the DCR comprising:
a non-transitory data storage configured to store instructions and the copy of the shared data; and
a processor, wherein the instructions are executable by the processor to cause the DCR to perform operations comprising:
receiving the indication from the CCI that the copy of shared data is out-of-date;
marking the shared data copy as out-of-date;
sending a request for an up-to-date copy of the shared data;
receiving the up-to-date copy of the shared data;
replacing the out-of-date copy of the shared data with the up-to-date copy of the shared data;
marking the replacement up-to-date shared data copy as valid; and
providing the shared data to the accelerator.
10. The system of claim 9 , wherein the shared data includes one or more data entries, wherein each data entry has a corresponding data value and data state.
11. The system of claim 10 , wherein the data state can be selected from the group consisting of valid, invalid, and out-of-date, wherein only data entries with the data state of out-of date or valid are provided to the accelerator.
12. The system of claim 9 , wherein the operations further comprise:
informing the accelerator that the shared data copy is out-of-date after marking the shared data copy as out-of-date; and
informing the accelerator that the shared data copy is valid after the replacement up-to-date shared data copy is marked valid.
13. The system of claim 9 , wherein the accelerator specifies a policy about receiving out-of-date shared data.
14. A dedicated cache register (DCR) comprising:
a processor;
non-transitory data storage, wherein the non-transitory data storage stores:
shared data; and
instructions that when executed by the processor cause the DCR to perform operations comprising:
determining that the shared data is out-of-date;
retrieving up-to-date shared data; and
providing the up-to-date shared data to an accelerator.
15. The DCR of claim 14 , wherein determining that the shared data is out-of-date comprises:
receiving an indication from a cache coherent interconnect (CCI) that the shared data is out-of-date.
16. The DCR of claim 14 , wherein the operations further comprise:
marking the shared data as out-of-date.
17. The DCR of claim 14 , wherein retrieving up-to-date shared data comprises:
sending a request for an up-to-date copy of the shared data; and
receiving the up-to-date copy of the shared data.
18. The DCR of claim 14 , wherein the operations further comprise:
replacing the out-of-date shared data with the up-to-date shared data.
19. The DRC of claim 14 , wherein the operations further comprise:
marking the up-to-date shared data as valid.
20. The DRC of claim 14 , wherein the shared data includes one or more data entries, wherein each data entry has a corresponding data value and a data state.
21. The DRC of claim 20 , wherein the data state can be selected from the group consisting of valid, invalid, and out-of-date.