Method and structure for receiving a micro device
A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.
1. A display comprising:
a display substrate;
an array of bottom conductive layers on the display substrate;
a passivation layer spanning across the display substrate and directly over the array of bottom conductive layers
a corresponding array of vertical semiconductor-based LEDs bonded to the array of bottom conductive layers, and embedded within the passivation layer;
wherein the passivation layer laterally surrounds a quantum well within each vertical semiconductor-based LED, and a top surface of the passivation layer does not cover a top surface of each vertical semiconductor-based LED; and
one or more top conductive layers spanning directly over the passivation layer and the vertical semiconductor-based LEDs, and in electrical contact with the vertical semiconductor-based LEDs.
2. The display of claim 1 , wherein the passivation layer comprises a thermoset material.
3. The display of claim 1 , wherein the one or more top conductive layers are in electrical contact with one or more electrode lines.
4. The display substrate of claim 1 , wherein each vertical semiconductor-based LED comprises sidewalls and a conformal dielectric barrier layer spanning along the sidewalls.
5. The display substrate of claim 4 , wherein the conformal dielectric barrier layer is 50-600 angstroms thick.
6. The display substrate of claim 5 , wherein the conformal dielectric barrier layer comprises Al 2 O 3 .
7. The display substrate of claim 1 , wherein the array of vertical semiconductor-based LEDs is bonded to the array of bottom conductive layers with a corresponding array of bonding layers.
8. The display substrate of claim 7 , wherein each bonding layer in the array of bonding layers is an alloy bonding layer.
9. The display substrate of claim 8 , wherein each alloy bonding layer is an alloy of a first bonding layer on a corresponding vertical semiconductor-based LED with a second bonding layer on a corresponding bottom conductive layer.
10. The display substrate of claim 9 , wherein the alloy bonding layer has a higher melting temperature than both of the first bonding layer and the second bonding layer.
11. The display of claim 1 , wherein the display substrate has a pixel density of greater than 300 pixels per inch.
12. The display substrate of claim 11 , wherein each vertical semiconductor-based LED has a maximum width of 1 to 100 μm.
13. The display substrate of claim 11 , wherein each vertical semiconductor-based LED has a maximum width of 1 to 10 μm.
14. The display substrate of claim 1 , wherein the display substrate includes active matrix display circuitry.
15. The display of claim 14 , wherein the active matrix display circuitry includes thin film transistors.
16. The display of claim 1 , further comprising a second passivation layer over the display substrate and underneath the passivation layer, wherein the second passivation layer includes an array of opening exposing the array of bottom conductive layers.
17. The display substrate of claim 16 , wherein the second passivation layer comprises a material selected form the group consisting of silicon oxide (SiO 2 ), silicon nitride (SiN x ), poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polyimide, and polyester.