Method and apparatus for determining metric for selective caching

1. A method for determining a metric for selective caching, comprising:

determining a result of an access to a cache for at least one tracked attribute;

determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result;

comparing the count value for the at least one tracked attribute with at least one threshold associated with the at least one tracked attribute; and

assigning the metric represented as at least one bit in the cache to a cache line corresponding to the translation look-aside buffer entry when the count value for the at least one tracked attribute exceeds the at least one threshold associated with the at least one tracked attribute and the result of next access to the cache for the at least one tracked attribute is a miss.

2. The method as claimed in claim 1 , wherein

one of the at least one tracked attribute comprises a miss; and

the determining a count value for the miss attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result comprises increasing the count value when the access to the cache is a miss.

3. The method as claimed in claim 1 , wherein

one of the at least one tracked attribute comprises a hit; and

the determining a count value for the hit attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result comprises increasing the count value when the access to the cache is a hit.

4. The method as claimed in claim 1 , wherein the determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result comprises:

determining a count value for the at least one tracked attribute in a sub-page of translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result.

5. The method as claimed in claim 1 , wherein

one of the at least one tracked attribute comprises an access to a slower memory unit or a slower cache unit in a non-uniform memory access architecture; and

the determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result comprises increasing the count value when the access to the cache is to the slower memory unit or the slower cache unit.

6. The method as claimed in claim 1 , further comprising:

determining the at least one threshold associated with the at least one tracked attribute in accordance with a cache characteristics to be optimized.

7. The method as claimed in claim 1 , further comprising:

detecting an event triggering clearing of the metric associated with at least one cache line; and

applying the metric clearing policy in response to the detecting via the translation look-aside buffer.

8. The method as claimed in claim 7 , wherein the count value for the at least one tracked attribute comprise a plurality of count values; and

the applying the metric clearing policy in response to the detecting via the translation look-aside buffer comprises resetting at least one count value in the translation look-aside buffer entry associated with the at least one cache line.

9. The method as claimed in claim 7 , wherein the count value for the at least one tracked attribute comprise a plurality of count values; and

the applying the metric clearing policy in response to the detecting comprises decrementing at least one count value in the translation look-aside buffer entry associated with the at least one cache line.

10. The method as claimed in claim 1 , further comprising:

detecting a need to evict the translation look-aside buffer entry; and

evicting the translation look-aside buffer entry with the lowest count value tracking the at least one tracked attribute comprising hit.

11. The method as claimed in claim 1 , wherein the selective caching comprises:

assigning to the at least one cache line with the metric the highest protection status;

assigning to the cache lines without the metric protection status in accordance with a cache eviction policy; and

evicting a cache line in accordance with the cache eviction policy starting with the cache lines with the lowest protection status.

12. The method as claimed in claim 11 , wherein the assigning to the at least one cache line with the metric the highest protection status comprises:

establishing rank of the metric in accordance with a value of a plurality of the sticky bits.

13. The method as claimed in claim 11 , wherein the assigning to the cache lines without the metric protection status in accordance with a cache eviction policy comprises:

assigning cache lines without the metric with not recently used bits set to one high protection status; and

assigning cache lines without the metric with not recently used bits set to zero low protection status.

14. An apparatus for determining metric for selective caching, comprising:

a multi-processor unit;

at least one cache communicatively connected to the multi-processor unit; and

at least one translation look-aside buffer communicatively connected to the multi-processor unit, wherein

each processor core in the multi-processor unit is configured to

determine a result of an access to a cache for at least one tracked attribute;

determine a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result;

compare the count value for the at least one tracked attribute with at least one threshold associated with the at least one tracked attribute; and

assign the metric represented as at least one bit in the cache to a cache line corresponding to the translation look-aside buffer entry when the count value for the at least one tracked attribute exceeds the at least one threshold associated with the at least one tracked attribute and the result of next access to the cache for the at least one tracked attribute is a miss.

15. The apparatus as claimed in claim 14 , wherein one of the at least one tracked attribute comprises a miss; and wherein

each processor core determines a count value for the miss attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result by being configured to increase the count value when the access to the cache is a miss.

16. The apparatus as claimed in claim 14 , wherein one of the at least one tracked attribute comprises a hit; and

each processor core determines a count value for the hit attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result by being configured to increase the count value when the access to the cache is a hit.

17. The apparatus as claimed in claim 14 , wherein each processor core determines a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result by being configured to:

determine a count value for the at least one tracked attribute in a sub-page of translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result.

18. The apparatus as claimed in claim 14 , wherein

one of the at least one tracked attribute comprises an access to a slower memory unit or a slower cache unit in a non-uniform memory access architecture; and

each processor core determines a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result by being configured to increase the count value when the access to the cache is to the slower memory unit or the slower cache unit.

19. The apparatus as claimed in claim 14 , wherein each processor core is further configured to set the at least one threshold associated with the at least one tracked attribute in accordance with a cache characteristics to be optimized.

20. The apparatus as claimed in claim 14 , each processor core is further configured to:

detect an event triggering clearing of the metric associated with at least one cache line; and

apply the metric clearing policy in response to the detecting via the translation look-aside buffer.

21. The apparatus as claimed in claim 20 , wherein the count value for the at least one tracked attribute comprise a plurality of count values; and

each processor core applies the metric clearing policy in response to the detecting via the translation look-aside buffer by being configured to:

reset at least one count value in the translation look-aside buffer entry associated with the at least one cache line.

22. The apparatus as claimed in claim 20 , wherein the count value for the at least one tracked attribute comprise a plurality of count values; and

each processor core applies the metric clearing policy in response to the detecting by being configured to:

decrement at least one count value in the translation look-aside buffer entry associated with the at least one cache line.

23. The apparatus as claimed in claim 14 , wherein each processor core is further configured to:

detect a need to evict a translation look-aside buffer entry; and

evict the translation look-aside buffer entry with the lowest count value tracking the at least one tracked attribute comprising hit.

24. The apparatus as claimed in claim 14 , wherein each processor core applies the selective caching by being configured to:

assign to the at least one cache line with the metric the highest protection status;

assign to the cache lines without the metric protection status in accordance with a cache eviction policy; and

evict a cache line in accordance with the cache eviction policy starting with the cache lines with the lowest protection status.

25. The apparatus as claimed in claim 24 , wherein each processor core assigns to the cache lines without sticky property protection status in accordance with a cache eviction policy by being configured to:

assign cache lines without the metric with not recently used bits set to one high protection status; and

assign cache lines without the metric with not recently used bits set to zero low protection status.

26. The apparatus as claimed in claim 14 , wherein each processor core assigns to the at least one cache line with the metric the highest protection status by being configured to:

establishing rank of the metric in accordance with a value of a plurality of the sticky bits.