Patent Assignment
Reel/Frame 051948/0807
Assignment of Assignor's Interest
Recorded: 2020-02-17
Pages: 76
Assignor
CAVIUM, LLC
Executed: 2019-12-31
Assignee
CAVIUM INTERNATIONAL
PO BOX 1350, CLIFTON HOUSE, 75 FORT STREET, GRAND CAYMAN, KYI-1108, CAYMAN ISLANDS
Covered Properties
(868)
Synchronization Circuit for Transferring Pointer Between Two Asynchronous Circuits
Patent:
6,055,285 →
Application:
08/971,387 →
State Dependent Synchronization Circuit Which Synchronizes Leading and Trailing Edges of Asynchronous Input Pulses
Patent:
6,163,550 →
Application:
08/972,117 →
Ofdm Receiving System
Patent:
6,151,295 →
Application:
09/030,865 →
Interface Module with Protection Circuit and Method of Protecting an Interface
Patent:
6,167,321 →
Application:
09/104,731 →
High Performance Switching
Patent:
6,597,691 →
Application:
09/386,109 →
Method and Circuit for Receiving Dual Edge Clocked Data
Patent:
6,317,842 →
Application:
09/249,873 →
Bus Driver with Data Dependent Drive Strength Control Logic
Patent:
6,229,845 →
Application:
09/257,803 →
Systems and Methods for Network and I/O Device Drivers
Patent:
6,470,397 →
Application:
09/280,506 →
Add-On Card with Automatic Bus Power Line Selection Circuit
Patent:
6,327,635 →
Application:
09/281,369 →
Host Adapter for Combining I/O Completion Reports and Method of Using the Same
Patent:
6,434,630 →
Application:
09/282,341 →
Method and Apparatus for Automatically Transferring I/O Blocks Between a Host System and a Host Adapter
High Performance Switch Fabric Element and Switch Systems
Patent:
6,697,359 →
Application:
09/346,793 →
High Performance Switch Fabric Element and Switch Systems
Fibre Channel Credit Extender and Repeater
Ipsec Performance Enhancement Using a Hardware-Based Parallel Process
Patent:
6,708,218 →
Application:
09/587,689 →
Hardware-Enforced Loop-Level Hard Zoning for Fibre Channel Switch Fabric
Secure Virtual Interface
Secure Virtual Interface
Secure Multiprotocol Interface
Interface for a Security Coprocessor
Patent:
6,789,147 →
Application:
10/025,512 →
Random Number Generator
Patent:
6,954,770 →
Application:
09/938,166 →
Router and Methods Using Network Addresses for Virtualization
Patent:
7,200,144 →
Application:
10/120,266 →
Router with Routing Processors and Methods for Virtualization
Router and Methods for Distributed Virtualization
System and Method of Providing Network Node Services
Method and Apparatus for Performing Computations and Operations on Data Using Data Steering
Method and Apparatus for Establishing Secure Sessions
Method and Apparatus for Montgomery Multiplication
Patent:
7,035,889 →
Application:
10/068,677 →
Method and Apparatus to Implement the Data Encryption Standard Algorithm
Patent:
7,076,059 →
Application:
10/052,054 →
On-Chip Inter-Subsystem Communication
On-Chip Inter-Subsystem Communication
Security System with an Intelligent Dma Controller
Subsystem Boot and Peripheral Data Transfer Architecture for a Subsystem of a System-on- Chip
Speculative Execution for Data Ciphering Operations
Patent:
7,260,217 →
Application:
10/092,328 →
Decoupled Architecture for Data Ciphering Operations
Patent:
7,305,567 →
Application:
10/234,895 →
System and Method for Eventless Detection of Newly Delivered Variable Length Messages from a System Area Network
System and Method for Improving Dynamic Range of Analog-to Digital Converters
Patent:
6,864,814 →
Application:
10/600,779 →
Method and System for Dynamically Assigning Domain Identification in a Multi-Module Fibre Channel Switch
Method and System for Primary Blade Selection in a Multi-Module Fibre Channel Switch
Method and System for Primary Blade Selection in a Multi-Module Fibre Channel Switch
System and Method for Optimizing Frame Routing in a Network
Patent:
7,334,046 →
Application:
10/212,425 →
Dual-Mode Network Storage Systems and Methods
Dual-Mode Network Storage Systems and Methods
Patent:
7,688,867 →
Application:
11/845,688 →
Zone Management in a Multi-Module Fibre Channel Switch
Patent:
7,397,768 →
Application:
10/241,153 →
Zone Management in a Multi-Module Fibre Channel Switch
Patent:
7,729,288 →
Application:
11/682,199 →
Method and System for Using Distributed Name Servers in Multi-Module Fibre Channel Switches
Patent:
7,362,717 →
Application:
10/263,858 →
Method and System for Reworking Ball Grid Arrays
Patent:
6,769,596 →
Application:
10/295,976 →
Method and Apparatus for Automatically Transferring I/O Blocks Between a Host System and a Host Adapter
Apparatus and Method for Repairing Logic Blocks
Patent:
6,861,865 →
Application:
10/387,151 →
Apparatus and Method for Repairing Logic Blocks
Patent:
7,205,785 →
Application:
11/040,266 →
Apparatus and Method for Data Deskew
Patent:
7,209,531 →
Application:
10/397,083 →
Method and System for Calibrating Scsi Expanders
Patent:
6,959,345 →
Application:
10/410,773 →
Transparent Ipsec Processing Inline Between a Framer and a Network Component
Apparatus and Method for Allocating Resources Within a Security Processing Architecture Using Multiple Queuing Mechanisms
Ipsec Performance Optimization
Apparatus and Method for Allocating Resources Within a Security Processing Architecture Using Multiple Groups
Apparatus and Method for Allocating Resources Within a Security Processor
Method and System for Processing Non-Data Frames in Host Bus Adapters
Patent:
6,961,784 →
Application:
10/417,523 →
On-Chip Packet-Based Interconnections Using Repeaters/Routers
Patent:
6,996,785 →
Application:
10/423,499 →
On-Chip Packet-Based Interconnections Using Repeaters/Routers
Patent:
7,543,250 →
Application:
11/283,210 →
Method and System for Providing a Virtual Universal Serial Port Interface and a Virtual Storage Interface
Patent:
7,424,419 →
Application:
10/445,695 →
Synchronizing Method and Apparatus
Method and System for Processing Network Data Packets
Patent:
7,515,612 →
Application:
10/619,719 →
Method and System for Processing Network Data Packets
Patent:
7,830,919 →
Application:
12/389,308 →
Method and System for Processing Network Data Packets
Patent:
7,403,542 →
Application:
10/620,040 →
Method and Apparatus for Testing Loop Pathway Integrity in a Fibre Channel Arbitrated Loop
Method and Apparatus for Accelerating Receive-Modify-Send Frames in a Fibre Channel Network
Method and Apparatus for Detecting and Removing Orphaned Primitives in a Fibre Channel Network
Method and Apparatus for Detecting and Removing Orphaned Primitives in a Fibre Channel Network
Method and System for Minimizing Disruption in Common-Access Networks
Method and System for Non-Disruptive Data Capture in Networks
Method and Apparatus for Improving Buffer Utilization in Communication Networks
Method and System for Selecting Virtual Lanes in Fibre Channel Switches
Method and System for Selecting Virtual Lanes in Fibre Channel Switches
Method and System for Fibre Channel Arbitrated Loop Acceleration
Method and Apparatus for Test Pattern Generation
Lun Based Hard Zoning in Fibre Channel Switches
Method and System for Detecting Congestion and Over Subscription in a Fibre Channel Network
Method and System for Providing Data Integrity in Storage Systems
Patent:
7,234,101 →
Application:
10/674,943 →
Method and System for Power Control of Fibre Channel Switches
Method and System for Power Control of Fibre Channel Switches
Method and System for Keeping a Fibre Channel Arbitrated Loop Open During Frame Gaps
Method and System for Keeping a Fibre Channel Arbitrated Loop Open During Frame Gaps
Method and System for Congestion Control Based on Optimum Bandwidth Allocation in a Fibre Channel Switch
Multi-Speed Cut Through Operation in Fibre Channel Switches
Multi-Speed Cut Through Operation in Fibre Channel Switches
Method and System for Routing Fibre Channel Frames
Method and System for Routing Fibre Channel Frames
Method and System for Improving Bandwidth and Reducing Idles in Fibre Channel Switches
Buffer to Buffer Credit Recovery for in-Line Fibre Channel Credit Extension Devices
Patent:
7,352,701 →
Application:
10/664,548 →
Method and System for Reducing Latency and Congestion in Fibre Channel Switches
Method and System for Programmable Data Dependant Network Routing
System and method for testing ball grid arrays
Patent:
7,009,413 →
Application:
10/683,622 →
Method and System for Minimizing Memory Corruption
Patent:
7,219,263 →
Application:
10/696,471 →
Method and System for Monitoring Events in Storage Area Networks
Patent:
7,103,504 →
Application:
10/719,077 →
Mosfet-Fused Nonvolatile Read-Only Memory Cell (Mofrom)
Patent:
6,949,423 →
Application:
10/723,004 →
Method and System for Distributing Credit in Fibre Channel Systems
Method and System for Buffer-to-Buffer Credit Recovery in Fibre Channel Systems Using Virtual and/or Pseudo Virtual Lanes
Method and System for Using Extended Fabric Features with Fibre Channel Switch Elements
Method and System for Using Extended Fabric Features with Fibre Channel Switch Elements
Patent:
7,990,975 →
Application:
12/697,994 →
Method and System for Using Extended Fabric Features with Fibre Channel Switch Elements
Patent:
8,644,317 →
Application:
13/177,314 →
Programmable Pseudo Virtual Lanes for Fibre Channel Systems
Programmable Pseudo Virtual Lanes for Fibre Channel Systems
Method and System for Managing Traffic in Fibre Channel Systems
Method and System for Managing Traffic in Fibre Channel Systems
Method and System for Routing and Filtering Network Data Packets in Fibre Channel Systems
Method and System for Preventing Deadlock in Fibre Channel Fabrics Using Frame Priorities
Method and System for Reducing Deadlock in Fibre Channel Fabrics Using Virtual Lanes
Method and System for Programmable Data Dependant Network Routing
Revision Control System for Large-Scale Systems Management
Patent:
7,231,410 →
Application:
10/797,977 →
Revision Control System for Large-Scale Systems Management
Pci - Express Slot for Coupling Plural Devices to a Host System
Method and System for Congestion Control in a Fibre Channel Switch
Direct Hardware Processing of Internal Data Structure Fields
Patent:
7,493,481 →
Application:
10/848,485 →
Method and System for Configuring Fibre Channel Ports
Method and System for Configuring Fibre Channel Ports
Method and System for Efficiently Recording Processor Events in Host Bus Adapters
Method and System for Host Device Event Synchronization
Fiber Optic Cable Retention and Guide Clip
Patent:
520,863 →
Application:
29/209,313 →
Integrated Fibre Channel Fabric Controller
Self-Triggering Outgoing Buffers
Patent:
7,308,535 →
Application:
10/927,170 →
Self-Trigerring Outgoing Buffers
Method and System for Efficiently Using Buffer Space
Method and System for Efficiently Using Buffer Space
Method and System for Processing Markers, Data Integrity Fields and Digests
Method and System for Optimizing Dma Channel Selection
Ensuring Buffer Availability
Patent:
7,895,390 →
Application:
10/940,355 →
Method and System for Processing Out of Order Frames
High Speed Fibre Channel Switch Element
High Speed Fibre Channel Switch Element
Method and System for Lun Remapping in Fibre Channel Networks
Method and System for Using Boot Servers in Networks
Methd and System for Using an in-Line Credit Extender with a Host Bus Adapter
Method and System for Transferring Data Directly Between Storage Devices in a Storage Area Network
Fibre Channel Transparent Switch for Mixed Switch Fabrics
Fibre Channel Transparent Switch for Mixed Switch Fabrics
Method and Apparatus for Efficient Determination of Status from Dma Lists
Patent:
7,512,721 →
Application:
10/963,287 →
Method and System for Dma Optimization in Host Bus Adapters
Store Instruction Ordering for Multi-Core Processor
Packet Queuing, Scheduling and Ordering
Local Scratchpad and Data Caching System
Method and System for High Speed Network Application
Direct Access to Low-Latency Memory
Method and Apparatus for Managing Write Back Cache
Address Translation in Fibre Channel Switches
Method and System for Testing Host Bus Adapters
Method and System for Managing Storage Area Networks
Patent:
7,496,745 →
Application:
11/346,106 →
Method and System for Sharing Input/Output Devices
Patent:
7,694,047 →
Application:
11/355,622 →
Tcp Time Stamp Processing in Hardware Based Tcp Offload
Method and System for Receiver Detection in Pci-Express Devices
Deterministic Finite Automata (Dfa) Instruction
Deterministic Finite Automata (Dfa) Processing
Content Search Mechanism That Uses a Deterministic Finite Automata (Dfa) Graph, a Dfa State Machine, and a Walker Process
Content Search Mechanism That Uses A Deterministic Finite Automata (DFA) Graph, A DFA State Machine, And A Walker Process
Content Search Mechanism That Uses A Deterministic Finite Automata (DFA) Graph, A DFA State Machine, And A Walker Process
Content Search Pattern Matching Using Deterministic Finite Automata (Dfa) Graphs
Selective Replication of Data Structures
Method and Apparatus for Reducing Host Overhead in a Socket Server Implementation
Method and Apparatus for Reducing Host Overhead in a Socket Server Implementation
Tcp Engine
Method and System for Asic Simulation
Method and System for High Speed Network Application
Gasket Retainer
Method and System for Testing Network Device Logic
Method and System for Synchronizing Bit Streams for Pci Express Devices
Patent:
7,230,549 →
Application:
11/222,592 →
Dedicated Application Interface for Network Systems
Patent:
7,639,715 →
Application:
11/223,693 →
Method and System for Dma Optimization
Patent:
7,577,773 →
Application:
11/222,936 →
Method and System for Designing a Flexible Hardware State Machine
Patent:
7,447,874 →
Application:
11/252,524 →
Method and System for Filtering Unknown Values in Asic Design Simulation
Patent:
7,630,876 →
Application:
11/257,693 →
Method and System for Managing Transmit Descriptors in a Networking System
Patent:
7,920,473 →
Application:
11/291,430 →
Method and System for Processing Network Data
Patent:
7,735,099 →
Application:
11/317,315 →
Method and system for port licensing in switches
Patent:
8,682,799 →
Application:
11/318,116 →
Method and System for Processing Dma Requests
Patent:
7,594,057 →
Application:
11/328,358 →
Method and System for Managing Storage Area Networks
Patent:
8,464,238 →
Application:
11/343,596 →
Method and System for Storing Frames in Networks
Patent:
7,668,978 →
Application:
11/357,515 →
Method and System for Managing Frame Flow in Fibre Channel Systems
Patent:
7,518,995 →
Application:
11/362,690 →
Method and System for Checking Frame-Length in Fibre Channel Frames
Patent:
7,548,560 →
Application:
11/363,365 →
Method and System for Motion Estimation with Multiple Vector Candidates
Method and System for Auto Routing Fibre Channel Class F Frames in a Fibre Channel Fabric
Patent:
7,525,968 →
Application:
11/376,955 →
Method and System for Dynamically Adjusting Data Transfer Rates in Pci-Express Devices
Patent:
7,461,195 →
Application:
11/378,838 →
Byte Level Protection in Pci-Express Devices
Method and System for Processing Arbitration Requests
Patent:
7,447,817 →
Application:
11/430,704 →
Method and System for Inter-Fabric Routing
Method and System for Managing Boot Trace Information in Host Bus Adapters
Patent:
7,610,482 →
Application:
11/477,161 →
Method and System for Testing Integrated Circuits
Patent:
7,379,837 →
Application:
11/491,357 →
System and Method for Managing Access to Adapter Features
Patent:
8,185,960 →
Application:
11/493,978 →
Method and System for Processing Network Information
Patent:
7,764,676 →
Application:
11/461,387 →
Method and System for Processing Asynchronous Event Notifications
Patent:
7,457,887 →
Application:
11/502,282 →
Method and System for Using Application Specific Integrated Circuits
Patent:
7,669,001 →
Application:
11/469,377 →
Method and System for Processing Network Information
Patent:
7,843,846 →
Application:
11/522,672 →
Method and System for Routing Network Information
Patent:
7,773,592 →
Application:
11/533,873 →
Method and System for Writing Network Data
Patent:
8,055,726 →
Application:
11/555,180 →
Method and System for Writing Network Data
Patent:
8,676,928 →
Application:
13/241,012 →
Method and System for Data Transfer
Patent:
8,601,179 →
Application:
11/555,123 →
Method and System for Routing Network Information
Patent:
7,613,816 →
Application:
11/560,317 →
Method and System for Real Time Compression and Decompression
Patent:
7,643,505 →
Application:
11/565,444 →
System and Method for Managing Interrupts
Patent:
7,549,005 →
Application:
11/615,329 →
Method and System for Quality of Service in Host Bus Adapters
Patent:
7,668,177 →
Application:
11/669,573 →
Compression and Decompression for Network Systems
Patent:
7,668,162 →
Application:
11/669,775 →
Compression and Decompression for Network Systems
Patent:
7,889,730 →
Application:
12/684,054 →
Congestion Reducing Reliable Transport Packet Retry Engine
Method and System for Processing Network Packets
Patent:
8,387,073 →
Application:
11/742,282 →
Method and System for Managing Metadata in Storage Virtualization Environment
Patent:
8,185,715 →
Application:
11/694,698 →
Method and Apparatus for Correcting Linear Error Phase of an Ofdm Signal
Method and System for Network Traffic Monitoring
Patent:
8,250,203 →
Application:
11/752,212 →
Method and System for Managing Ports in a Host Bus Adapter
Patent:
8,095,978 →
Application:
11/761,279 →
Method and System for Network Communication
Patent:
8,102,769 →
Application:
11/762,578 →
Method and System for Network Communication
Patent:
8,792,351 →
Application:
13/330,085 →
Method and System for Securing Network Data
Patent:
8,010,809 →
Application:
11/965,037 →
Method and System for Securing Network Data
Patent:
8,261,099 →
Application:
13/190,165 →
Power Management for Host Bus Adapters
Patent:
8,904,077 →
Application:
12/111,057 →
Method and System for Processing Layered Networking Protocol Packets
Patent:
8,411,677 →
Application:
11/842,830 →
Resistively Loaded Single Stage Differential Amplifier Having Zero Volt Common Mode Input
Method and System for Monitoring a Network Link in Network Systems
Patent:
7,903,558 →
Application:
11/864,651 →
Method and System for Monitoring a Network Link in Network Systems
Patent:
8,441,929 →
Application:
13/026,007 →
Graph Caching
Graph Caching
Intelligent Graph Walking
Method and System for Managing Network and Storage Data
Patent:
7,908,404 →
Application:
12/052,130 →
Method and Apparatus for Traversing a Compressed Deterministic Finite Automata (Dfa) Graph
Deterministic Finite Automata (Dfa) Graph Compression
Method and System for Processing Network and Storage Data
Patent:
7,720,064 →
Application:
11/963,566 →
Method and System for Processing Network and Storage Data
Patent:
8,225,004 →
Application:
12/751,955 →
System and Method for Assigning Network Device Port Address Based on Link Rate
Patent:
7,719,969 →
Application:
11/966,857 →
Method and System for Credit Management in a Networking System
Patent:
7,609,710 →
Application:
12/019,094 →
Method and System for Communicating with a Host Bus Adapter
Patent:
7,962,675 →
Application:
12/034,913 →
Secure Software and Hardware Association Technique
Method and System for Routing Frames in a Network
Patent:
8,116,206 →
Application:
12/037,847 →
Systems and Methods for Testing Device Ports in a Storage Area Network
Patent:
7,895,300 →
Application:
12/039,604 →
Method and System for Selection of Reference Picture and Mode Decision
System and Method for Optimizing Use of Channel State Information
System and Method for Optimizing Use of Channel State Information
Method and System for Network Port Addressing
Patent:
7,773,629 →
Application:
12/135,973 →
Single-Ended to Differential Converter
Method and System for Processing Network Packets
Patent:
8,296,386 →
Application:
12/489,241 →
Method and System for Processing Network Packets
Patent:
8,867,537 →
Application:
13/610,095 →
System and Methods for Locating Fpdu Headers When Markers Are Disabled
Patent:
7,765,317 →
Application:
12/165,464 →
Method and System for Network Communication
Patent:
8,351,442 →
Application:
12/505,430 →
Method and System for Accelerating Network Packet Processing
Patent:
8,793,399 →
Application:
12/536,336 →
Configurable Switch Element and Methods Thereof
Patent:
8,391,300 →
Application:
12/539,156 →
Configurable Switch Element and Methods Thereof
Patent:
8,976,800 →
Application:
13/758,543 →
Method and Apparatus for Content Based Searching
Emulation of Multiple Mdio Manageable Devices
Patent:
8,200,473 →
Application:
12/547,414 →
Computer Network Device and Method of Assembly
Patent:
7,667,985 →
Application:
12/200,649 →
Apparatus and Methods for Cooling Network Switches
Patent:
7,646,602 →
Application:
12/201,304 →
Apparatus and Methods for Cooling Network Switches
Patent:
7,675,750 →
Application:
12/201,359 →
Dll-Based Temperature Sensor
Deterministic Finite Automata Graph Traversal with Nodal Bit Mapping
Deterministic Finite Automata Graph Traversal With Nodal Bit Mapping
Traversal With Arc Configuration Information
Network Device Having Levers and Associated Methods
Patent:
7,907,414 →
Application:
12/410,294 →
Method and System for Network Switch Element
Method and System for Network Switch Element
Method and System for Taking a Network Port Offline
Patent:
9,094,343 →
Application:
12/412,050 →
Method and System for Port Negotiation
Patent:
7,907,546 →
Application:
12/411,176 →
Method and System for Tag Arbitration in Switches
Patent:
8,116,311 →
Application:
12/615,152 →
Method and System for Transmitting Flow Control Information
Patent:
8,089,971 →
Application:
12/423,626 →
Method and System for Multi-Level Switch Configuration
Patent:
8,060,682 →
Application:
12/415,873 →
Multiple core Session Initiation Protocol (SIP)
Method and System for Controlling Power Consumption in Network Nodes
Patent:
8,155,022 →
Application:
12/552,222 →
Method and System for Extended Port Addressing
Patent:
8,351,448 →
Application:
12/731,065 →
Method and System for Extended Port Addressing
Patent:
9,071,558 →
Application:
13/711,380 →
Network Device with Baffle for Redirecting Cooling Air and Associated Methods
Patent:
8,068,338 →
Application:
12/410,277 →
System and Methods for Inter-Driver Communication
Patent:
8,978,052 →
Application:
12/551,302 →
Method and System for Load Balancing in Networks
Patent:
8,705,351 →
Application:
12/774,574 →
Flexible Server Network Connection Upgrade Systems and Methods
Patent:
8,069,293 →
Application:
12/471,331 →
System and Method to Restore Maximum Payload Size in a Network Adapter
Patent:
8,996,730 →
Application:
13/447,652 →
System and Method to Process Event Reporting in an Adapter
Patent:
8,504,750 →
Application:
12/572,835 →
System and Method to Process Event Reporting in an Adapter
Patent:
9,043,519 →
Application:
13/856,848 →
System and Method for Mapping Functions to and from Network Devices Using Configuration Compatible with an Adapter by Remapping Plurality of Logical Ports of Adapter
Patent:
8,065,454 →
Application:
12/544,658 →
System and Method for Mapping Functions to and from Network Devices Using Configuration Compatible with an Adapter by Remapping Plurality of Logical Ports of Adapter
Patent:
8,225,018 →
Application:
13/221,737 →
Method and System for Routing Information in a Network
Patent:
8,706,905 →
Application:
12/859,690 →
System and Methods for Managing Virtual Adapter Instances
Patent:
8,671,228 →
Application:
12/572,810 →
Concurrent Transmit Processing
Patent:
7,970,927 →
Application:
12/651,270 →
Concurrent Transmit Processing
Patent:
8,275,903 →
Application:
13/111,475 →
System and Methods for Data Migration
Patent:
9,329,794 →
Application:
12/691,629 →
Method and Apparatus for Estimating Overshoot Power After Estimating Power of Executing Events
Method and Apparatus for Power Control
Method And Apparatus For Power Control
System and Methods for Presenting Storage
Patent:
8,406,152 →
Application:
12/730,139 →
System and Methods for Presenting Storage
Patent:
8,873,430 →
Application:
13/770,828 →
Systems and Methods for Bandwidth Scavenging Among a Plurality of Applications in a Network
Patent:
8,307,111 →
Application:
12/759,316 →
Systems and Methods for Bandwidth Scavenging Among a Plurality of Applications in a Network
Patent:
9,003,038 →
Application:
13/644,203 →
System and Method for Secure Device Key Storage
Method and Apparatus for a Virtual System on Chip
Method and Apparatus for a Virtual System on Chip
Method and Apparatus for Virtualization
Method and Apparatus for Virtualization
Method and Apparatus for a Virtual System on Chip
System and Method for Low-Latency Multimedia Streaming
Method and System for Communication with an Adapter
Patent:
8,315,268 →
Application:
12/795,563 →
System and Methods for Using a Dma Module for a Plurality of Virtual Machines
Patent:
8,250,252 →
Application:
12/826,105 →
System and Methods for Using a Dma Module for a Plurality of Virtual Machines
Patent:
8,392,629 →
Application:
13/489,016 →
Method and System for Communication Across Multiple Channels
Patent:
8,478,909 →
Application:
12/914,852 →
System and Method for Enabling Access to a Protected Hardware Resource
Method and System for Congestion Management in Networks
Patent:
8,441,922 →
Application:
13/216,598 →
System and Methods for Migrating Information from Source Storage to Destination Storage
Patent:
8,510,527 →
Application:
12/901,409 →
Ring Bus for Sharing Resources Among Multiple Engines
Patent:
8,301,817 →
Application:
12/902,020 →
Systems and Methods for Efficiently Processing Large Data Segments
Patent:
8,386,644 →
Application:
12/901,994 →
Selectable Initialization for Adapters
Patent:
8,566,573 →
Application:
12/941,621 →
Facilitating Communication Between Devices in a Network
Patent:
9,426,097 →
Application:
12/964,295 →
Dram Address Protection
Dram Address Protection
Messaging with Flexible Transmit Ordering
Messaging with Flexible Transmit Ordering
Messaging with Flexible Transmit Ordering
Level-Up Shifter Circuit
Level-Up Shifter Circuit for High Speed and Low Power Applications
Differential Amplifier with Duty Cycle Compensation
Differential Amplifier with De-Emphasis
Synchronized Clock Phase Interpolator
Memory Interface with Selectable Evaluation Modes
State Machine for Deskew Delay Locked Loop
Multi-Function Delay Locked Loop
Multi-Function Delay Locked Loop
Simulation System and Method Thereof
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Method and System for Application Isolation
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Regular Expression Processing Automaton
System and Method of Compression and Decompression
System And Method Of Compression And Decompression
Low latency rate control system and method
Low Latency Rate Control System and Method
On-Demand Intra-Refresh for End-to End Coded Video Transmission Systems
Compression with Adjustable Quality/Bandwidth Capability
Regex Compiler
Anchored Patterns
Anchored Patterns
Video encoder bit estimator for macroblock encoding
Video Encoder Bit Estimator for Macroblock Encoding
Method and System for Link Aggregation
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Method and System for Link Aggregation
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Method and System for Managing Network Elements
System and Method for Storing Lookup Request Rules in Multiple Memories
Packet Classification
Identifying Duplication in Decision Trees
Duplication in Decision Trees
Decision Tree Level Merging
Packet Classification
Method and Apparatus Encoding a Rule for a Lookup Request in a Processor
System and Method for Rule Matching in a Processor
System and Method for Rule Matching in a Processor
Lookup Front End Packet Input Processor
Lookup Front End Packet Input Processor
Lookup Front End Packet Input Processor
Lookup Front End Packet Output Processor
Lookup Front End Packet Output Processor
Method and Apparatus for Managing Transport Operations to a Cluster Within a Processor
Method and Apparatus for Managing Transfer of Transport Operations from a Cluster in a Processor
Method and Apparatus for Assigning Resources Used to Manage Transport Operations Between Clusters Within a Processor
Method and Apparatus for Managing Processing Thread Migration Between Clusters Within a Processor
Method And Apparatus For Managing Processing Thread Migration Between Clusters Within A Processor
Incremental Update
Rule Modification in Decision Trees
Incremental Update Heuristics
Method and Apparatus for Multiple Access of Plural Memory Banks
On-Chip Memory (Ocm) Physical Bank Parallelism
Work Migration in a Processor
Work Migration in a Processor
Lookup Cluster Complex
Lookup Cluster Complex
Lookup Cluster Complex
Phased Bucket Pre-Fetch in a Network Processor
Phased Bucket Pre-Fetch in a Network Processor
Methods and Systems for Processing Network Information
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Method and System for Memory Management
Method and System for Memory Management
Flexible Edge Access Switch and Associated Methods Thereof
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Electronic Devices Having Cooling Module with Direction-Configurable Airflow
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Qos Based Dynamic Execution Engine Selection
Qos Based Dynamic Execution Engine Selection
Processor with Dedicated Virtual Functions and Dynamic Assignment of Functional Resources
Processor With Efficient Work Queuing
Packet Priority in a Network Processor
Bit Error Rate Impact Reduction
System and Method to Provide Non-Coherent Access to a Coherent Memory System
System and Method to Provide Non-Coherent Access to a Coherent Memory System
System and Method to Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports
System And Method To Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports
Word Boundary Lock
Word Boundary Lock
Multi-Protocol Serdes Phy Apparatus
Input Output Bridging
Input Output Bridging
Systems and Methods for Sending and Receiving Information via a Network Device
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Systems and Methods for Sending and Receiving Information via a Network Device
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Packet Traffic Control in a Network Processor
Network Processor with Distributed Trace Buffers
Work Request Processor
Work Request Processor
Tools, Systems, and Methods for Removing Connectors from Ports in a Network Device
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Multi-Core Interconnect in a Network Processor
Reverse Nfa Generation and Processing
Reverse Nfa Generation and Processing
Method and System for Offloading Copy on Write Operations
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High Speed Variable Bandwidth Ring-Based System
Intelligent Adapter for Providing Storage Area Network Access and Access to a Local Storage Device
Intelligent Adapter for Maintaining Cache Coherency
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In-Band Management Using an Intelligent Adapter and Methods Thereof
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Method and System for Writing Tag and Data
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Methods and Systems for an Intelligent Storage Adapter Used for Both San and Local Storage Access
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System and Method for High Speed Multiple Buffer Allocation
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Method and System for Communication Between a Computing System and a Device
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Method and System for Communication Between a Computing Device and a Peripheral Device
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Method and System for Arbitration Verification
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Method and System for Signal Equalization in Communication Between Computing Devices
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Method and System for Communication Using Multiple Dma Channels
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Method and System for Communication with Peripheral Devices
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System and Methods for Managing Networks
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Method and System for Variable Length Tag Processing
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Method and System for Detecting Loss of Synchronization in Ports
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Memory Devices for Network Devices and Associated Methods
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Systems and Methods for Processing Information by a Network Device
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System and Method for Sharing Logic in a Network Device
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Network Device Scheduler and Methods Thereof
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Network Device Scheduler and Methods Thereof
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Systems and Methods for Hard Zoning in Networks
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Cut-Through Routing for Network Devices
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Systems and Methods for Modifying Frames in a Network Device
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Systems and Methods for Quality of Service in Networks
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Systems and Methods for Routing by Network Devices
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Systems and Methods for Packet Grouping in Networks
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Systems and Methods for Using Tcams in Network Devices
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Systems and Methods for Rate Matching in Networks Utilizing a Strobe Counter
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Network Devices Having Configurable Receive Packet Queues and Related Methods
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Network Devices Having Configurable Receive Packet Queues and Related Methods
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Method and System for Programmable Delay Before Transmission Pausing
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Smoothing Fifo and Methods Thereof
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Method and System for Auto-Negotiation
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Systems and Methods for Primitive Sequence Capture and Retransmission in a Network Device
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Method and System for Using Lane Alignment Markers
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Systems and Methods for Identifying Port Protocols Using Leds
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Methods and Systems for Processing Commands by a Device Interfacing with a Computing System
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Method and System for Inserting Cookies in I/O Commands
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Method and System for Frame Aggregation
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Method and System of Configuring Virtual Function in Peripheral Devices
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Method and System for Using Asymetric Transfer Rates in Receive and Transmit Paths of a Network
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Apparatus and Method for Processing Alternately Configured Longest Prefix Match Tables
Apparatus and Method for Processing Alternately Configured Longest Prefix Match Tables
Apparatus and Method for Packet Memory Datapath Processing in High Bandwidth Packet Processing Devices
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Apparatus and Method for Media Access Control Scheduling with a Priority Calculation Hardware Coprocessor
Batch Incremental Update
Apparatus and Method for Media Access Control Scheduling with a Sort Hardware Coprocessor
Merging Independent Writes, Separating Dependent And Independent Writes, And Error Roll Back
NSP Manager
Multi-Host Processing
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Compiler with Mask Nodes
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Method and an Accumulator Scoreboard for Out-of-Order Rule Response Handling
Scope in Decision Trees
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Scope In Decision Trees
Method and Apparatus for Scheduling Rule Matching in a Processor
Packet Extraction Optimization in a Network Processor
Method and Apparatus for Data Packet Integrity Checking in a Processor
Apparatus and Method for Table Search with Centralized Memory Pool in a Network Switch
Method and System for Transmitting Information from a Network Device
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Method and System for Processing Write Requests
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Apparatus and Method for Uniquely Enumerating Paths in a Parse Tree
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Method and System for Configuring Network Devices
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Methods and Systems for Advertsing Available Credit at Memory of Network Device Ports Based on Temperature
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Method and System for Processing Information at Peripheral Devices
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Scannable Flop with a Single Storage Element
Multiplexer Flop
Method and Apparatus for Processing Finite Automata
Method and System for Determining Drop Eligibility of Network Information
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9,154,455 →
Application:
14/014,803 →
Clock Gated Delay Line Based On Setting Value
Generating a Non-Deterministic Finite Automata (NFA) Graph for Regular Expression Patterns with Advanced Features
System and Method to Traverse a Non-Deterministic Finite Automata (NFA) Graph Generated for Regular Expression Patterns with Advanced Features
Method and Apparatus for Compilation of Finite Automata
Clock Distribution Circuit with Distributed Delay Locked Loop
Apparatus and Method for Time Stamping Packets Across Several Nodes in a Network
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Apparatus and Method for Optimizing the Number of Accesses to Page-Reference Count Storage In Page Link List Based Switches
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Apparatus and Method for Accelerated Page Link List Processing in a Packet Processor Operating at Wirespeed
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Apparatus and Method for Accelerated Page Link List Processing in a Packet Processor Operating at Wirespeed
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Method for Storing and Retrieving Packets in High Bandwidth and Low Latency Packet Processing Devices
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Systems and Methods for Routing Multicast Packets
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Method and System for Data Integrity
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Application:
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Memory Interface With Integrated Tester
Merged TLB Structure For Multiple Sequential Address Translations
Translation Bypass In Multi-Stage Address Translation
Collapsed Address Translation With Multiple Page Sizes
Collapsed Address Translation with Multiple Page Sizes
Maintenance Of Cache And Tags In A Translation Lookaside Buffer
Dynamically Adjusting Supply Voltage Based On Monitored Chip Temperature
Method and Apparatus for Calibrating an Input Interface
Method and Apparatus for Amplifier Offset Calibration
Method and Apparatus for Reference Voltage Calibration in a Single-Ended Receiver
Auto-Blow Memory Repair
Clock Multiplexing and Repeater Network
Systems and Methods for Quality of Service for Link Aggregation Groups
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Application:
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Protocol Switching over Multi-Network Interface
Method And Apparatus For Conditional Storing Of Data Using A Compare-And-Swap Based Approach
Method And Apparatus For Supporting Wide Operations Using Atomic Sequences
Data Strobe Generation
Method and Apparatus for Aligning Signals
Method and System for Data Integrity in Tcams
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Systems and Methods for High Speed Data Processing at a Network Port
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Timers and Methods Thereof for Computing Devices
Patent:
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Application:
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Method and Apparatus to Represent a Processor Context with Fewer Bits
Virtualized Network Interface for Tcp Reassembly Buffer Allocation
Method and System for Remote Cache Direct Data Placement
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Application:
14/088,082 →
Systems and Methods for Specifying. Modeling, Implementing and Verifying Ic Design Protocols
Virtualized Network Interface for Remote Direct Memory Access Over Converged Ethernet
Virtualized Network Interface for Lockdown and Overlay of Data in Transmitted Packets
Method and an Apparatus for Virtualization of a Quality-Of-Service
System and a Method for a Remote Direct Memory Access Over Converged Ethernet
Method and an Apparatus for Memory Address Allignment
Method and an Apparatus for Converting Interrupts into Scheduled Events
System for and Method of Combining Cmos Inverters of Multiple Drive Strengths to Create Tune-Able Clock Inverters of Variable Drive Strengths in Hybrid Tree-Mesh Clock Distribution Networks
System for and Method of Placing Clock Stations Using Variable Drive-Strength Clock Drivers Built Out of a Smaller Subset of Base Cells for Hybrid Tree-Mesh Clock Distribution Networks
System for and Method of Tuning Clock Networks Constructed Using Variable Drive-Strength Clock Inverters with Variable Drive-Strength Clock Drivers Built Out of a Smaller Subset of Base Cells
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Matrix of on-Chip Routers Interconnecting a Plurality of Processing Engines and a Method of Routing Using Thereof
Look-Aside Processor Unit with Internal and External Access for Multicore Processors
Apparatus and Method for Interrupt Collecting and Reporting Status and Delivery Information
Method and Apparatus for Processing of Finite Automata
Method and Apparatus for Parallel and Conditional Data Manipulation in a Software-Defined Network Processing Engine
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Method and System for Skipping Over Group(S) of Rules Based on Skip Group Rule
Multi-Rule Approach to Encoding a Group of Rules
Packet Parsing Engine
Methods and Systems for Resource Management in a Single Instruction Multiple Data Packet Parsing Cluster
Processing Request Keys Based on a Key Size Supported by Underlying Processing Elements
Method and Apparatus for Compiling Search Trees for Processing Request Keys Based on a Key Size Supported by Underlying Processing Elements
Condition Code Approach for Comparing Rule and Packet Data That Are Provided in Portions
Floating Mask Generation for Network Packet Flow
Methods and Systems for Distribution of Packets Among Parsing Clusters
Block Mask Register Key Processing by Compiling Data Structures to Traverse Rules and Creating a New Rule Set
Method and System for Managing Storage Reservation
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Application:
14/165,100 →
Method and System for Communication in a Virtual Machine Environment
Patent:
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Application:
14/166,082 →
Method And Apparatus For Optimizing Finite Automata Processing
Finite Automata Processing Based on a Top of Stack (TOS) Memory
Method and an Apparatus for Work Packet Queuing, Scheduling, and Ordering with Conflict Queuing
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14/170,955 →
Publication:
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Method and an Apparatus for Work Request Arbitration in a Network Processor
Method and an Apparatus for Pre-Fetching and Processing Work for Procesor Cores in a Network Processor
Multiple Ethernet Ports and Port Types Using a Shared Data Path
Multiple Ethernet Ports and Port Types Using a Shared Data Path
Apparatus and Method for Software Enabled Access to Protected Hardware Resources
Method and Apparatus for Memory Access Management
Cdr Voter with Improved Frequency Offset Tolerance
System on Chip Link Layer Protocol
Partitioned Error Code Computation
Packet Scheduling in a Network Processor
Packet Output Processing
Method And Apparatus For Power Gating Hardware Components In A Chip Device
Packet Shaping in a Network Processor
Method and System for Port Trunking
Patent:
9,588,920 →
Application:
14/193,658 →
Method and Apparatus for Memory Allocation in a Multi-Node System
Inter-Chip Interconnect Protocol for a Multi-Chip System
Method and System for Ordering I/O Access in a Multi-Node Environment
Method and System for Work Scheduling in a Multi-Chip System
Method for Work Scheduling in a Multi-Chip System
Method and System for Operating System Recovery from a Network Device Including User Selectable Options for Storing an Os Image in Local Storage of a Caching Device
Patent:
9,384,008 →
Application:
14/230,768 →
Processing of Finite Automata Based on a Node Cache
Processing Of Finite Automata Based On Memory Hierarchy
Memory Management for Finite Automata Processing
Compilation of Finite Automata Based on Memory Hierarchy
System and Method for Automated Functional Coverage Generation and Management for Ic Design Protocols
Method and System for Virtual Machine Communication
Patent:
9,483,290 →
Application:
14/264,927 →
Systems and Methods for Managing Direct Memory Access Operations
Patent:
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Application:
14/264,957 →
Systems and Methods for Enabling Access to Extensible Storage Devices Over a Network as Local Storage via Nvme Controller
Systems and Methods for Supporting Hot Plugging of Remote Storage Devices Accessed Over a Network via Nvme Controller
Systems and Methods for Supporting Migration of Virtual Machines Accessing Remote Storage Devices Over Network via Nvme Controllers
Systems and Methods for Enabling Access to Extensible Remote Storage Over a Network as Local Storage via a Logical Storage Controller
Method and Apparatus for Analytics in a Network Switch
Method and Apparatus for Table Aging in a Network Switch
Method and Apparatus for Table Aging in a Network Switch
Systems and Methods for Secured Backup of Hardware Security Modules for Cloud-Based Web Services
Hierarchical Statistically Multiplexed Counters and a Method Therof
Hierarchical Statisically Multiplexed Counters and a Method Thereof
Hierarchical Statisically Multiplexed Counters and a Method Thereof
Methods and Systems for Automatically Adding Intelligent Storage Adapters to a Cluster
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9,423,980 →
Application:
14/302,706 →
Method of Using Bit Vectors to Allow Expansion and Collapse of Header Layers Within Packets for Enabling Flexible Modifications and an Apparatus Thereof
Method of Using Bit Vectors to Allow Expasion and Collapse of Header Layers Within Packets for Enabling Flexible Modifications and an Apparatus Thereof
Method of Extracting Data from Packets and an Apparatus Thereof
Method of Identifying Internal Destinations of Network Packets and an Apparatus Thereof
Method of Identifying Internal Destinations of Network Packets and an Apparatus Thereof
Method of Dynamically Renumbering Ports and an Apparatus Thereof
Method of Dynamically Renumbering Ports and an Apparatus Thereof
Method of Reducing Latency in a Flexible Parser and an Apparatus Thereof
Method of Handling Large Protocol Layers for Configurable Extraction of Layer Information and an Apparatus Thereof
Method of Forming a Hash Input from Packet Contents and an Apparatus Thereof
Method of Splitting a Packet into Individual Layers for Modification and Intelligently Stitching Layers Back Together After Modification and an Apparatus Thereof
Method of Using Generic Modification Instructions to Enable Flexible Modifications of Packets and an Apparatus Thereof
Method of Using a Unique Packet Identifier to Identify Structure of a Packet and an Apparatus Thereof
Method of Representing a Generic Format Header Using Continuous Bytes and an Apparatus Thereof
Method of Modifying Packets to a Generic Format for Enabling Programmable Modifications and an Apparatus Thereof
Methods and Systems for Processing Task Management Functions in a Cluster Having an Intelligent Storage Adapter
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9,436,654 →
Application:
14/312,130 →
Engine Architecture for Processing Finite Automata
Engine Architecture for Processing Finite Automata
Methods and Systems for Reliable Network Communication
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Application:
14/663,912 →
Managing Instruction Order in a Processor Pipeline
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Publication:
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Managing Instruction Order in a Processor Pipeline
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Publication:
US US20160011877A1
Baseboard Interconnection Device, System and Method
Methods and Systems for Using an Intelligent Storage Adapter for Replication in a Clustered Environment
Patent:
9,477,424 →
Application:
14/339,086 →
Integrated Fabric Adapter and Associated Methods Thereof
Patent:
9,819,515 →
Application:
14/724,273 →
Method and an Apparatus for Co-Processor Data Plane Virtualization
Methods and Systems for Improved Caching with Data Recovery
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9,477,414 →
Application:
14/464,535 →
Methods and Systems for Performing a Read Ahead Operation Using an Intelligent Storage Adapter
Patent:
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Application:
14/470,309 →
Methods and Systems for Improved Data Caching in a Virtualized Environment
Patent:
9,330,010 →
Application:
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Method and System for Transmitting Information in a Network
Patent:
9,936,003 →
Application:
14/473,524 →
Method and Apparatus for Managing Global Chip Power on a Multicore System on Chip
Method and Apparatus for Managing Global Chip Power on a Multicore System on Chip
Method and Apparatus for Managing Global Chip Power on a Multicore System on Chip
Fast Hardware Switchover in a Control Path in a Network Asic
Fast Hardware Switchover in a Control Path in a Network Asic
Multicast Replication Engine of a Network Asic and Methods Thereof
Hierarchical Hardware Linked List Approach for Multicast Replication Engine in a Network Asic
Hierarchical Hardware Linked List Approach for Multicast Replication Engine in a Network Asic
Hierarchical Hardware Linked List Approach for Multicast Replication Engine in a Network Asic
Method and Apparatus for Improving Data Integrity Using Compressed Soft Information
Session Based Packet Mirroring in a Network Asic
Session Based Packet Mirroring in a Network Asic
Method and Apparatus for Quantizing Soft Information Using Non-Linear LLR Quantization
Method and Apparatus for Quantizing Soft Information Using Linear Quantization
Methods and Systems for Efficient Cache Mirroring
Patent:
9,460,017 →
Application:
14/498,580 →
Systems and Methods for Defining Storage
Patent:
10,129,162 →
Application:
14/716,689 →
Systems and Methods for Allowing Flexible Chip Configuration by External Entity While Maintaining Secured Boot Environment
Flexible Instruction Execution in a Processor Pipeline
Flexible Instruction Execution in a Processor Pipeline
Apparatus and a Method of Detecting Errors on Registers
Two Modes of a Configuration Interface of a Network Asic
Method of Implementing a Network Asic in a Network Device
Smart Holding Registers to Enable Multiple Register Accesses
Multiple-Interrupt Propagation Scheme in a Network Asic
Methods and Systems for a Multi-Function Adapter
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9,936,021 →
Application:
14/530,388 →
Methods and Systems for Accessing Storage Using a Network Interface Card
Hybrid Wildcard Match Table
Hybrid Wildcard Match Table
Adder Decoder
Register Access Control Among Multiple Devices
Programmable Validation of Transaction Requests
Arbitrated Access To Resources Among Multiple Devices
Programmable Ordering and Prefetch
Packet Scheduling Using Hierarchical Scheduling Process
Frequency Division Clock Alignment
Method and Apparatus for Performing a Weighted Queue Scheduling Using a Set of Fairness Factors
Filtering Translation Lookaside Buffer Invalidations
Managing Buffered Communication Between Sockets
Managing History Information for Branch Prediction
Testing Semiconductor Devices
High Performance Shifter Circuit
Controlled Multi-Step De-Alignment of Clocks
Instruction Ordering for in-Progress Operations
Instruction Ordering for in-Progress Operations
Managing Buffered Communication Between Cores
Controlled Dynamic De-Alignment of Clocks
Managing Skew in Data Signals with Multiple Modes
Managing Skew in Data Signals with Adjustable Strobe
Managing Skew in Data Signals
Approach for Interfacing a Pipeline with Two or More Interfaces in a Processor
Apparatus and Method for Distributed Instruction Trace in a Processor System
Network Switching with Co-Resident Data-Plane and Network Interface Controllers
Network Switching with Co-Resident Data-Plane and Network Interface Controllers
Apparatus and Method for a Multi-Entity Secure Software Transfer
Translation Lookaside Buffer Invalidation Suppression
Caching Tlb Translations Using a Unified Page Table Walker Cache
Translation Lookaside Buffer Management
Distributed Interrupt Scheme in a Multi-Processor System
Debug Interface for Multiple Cpu Cores
Method and System for Improved Load Balancing of Received Network Traffic
Sharing Resources in a Multi-Context Computing System
Implementing 128-Bit Simd Operations on a 64-Bit Datapath
Management of an Over-Subscribed Shared Buffer
Distributed Timer Subsystem
Automatic Data Rate Matching
Carry Chain for Simd Operations
Bypass Fifo for Multiple Virtual Channels
Distributing Resource Requests in a Computing System
Frequency Division Clock Alignment Using Pattern Selection
Distributed Timer Subsystem Across Multiple Devices
Method and System for Compressing Data for a Translation Look Aside Buffer (Tlb)
Method and System for Compressing Data for a Translation Look Aside Buffer (Tlb)
Method to Measure Edge-Rate Timing Penalty of Digital Integrated Circuits
Methods and Systems for Efficient Data Transmission in a Data Center by Reducing Transport Layer Processing
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9,674,303 →
Application:
14/548,040 →
Systems and Methods for Hardware Accelerated Timer Implementation for Openflow Protocol
Systems and Methods for Hardware Accelerated Metering for Openflow Protocol
Network Switching with Layer 2 Switch Coupled Co-Resident Data-Plane and Network Interface Controllers
Methods and Systems for Parallel Distributed Computation
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9,396,023 →
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14/585,761 →
Methods and Systems for Efficient Caching Using an Intelligent Storage Adapter
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14/593,898 →
Methods and Systems for Direct Memory Access Operations
Patent:
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Application:
14/597,030 →
Methods and Systems for Controlling Transmission Rates in Networks
Patent:
9,426,084 →
Application:
14/609,945 →
Automated Flip-Flop Insertions in Physical Design Without Perturbation of Routing
Testbench Builder, System, Device and Method Having Agent Loopback Functionality
Testbench Builder, System, Device and Method Including a Dispatcher
Testbench Builder, System, Device and Method
Testbench Builder, System, Device and Method Including a Generic Monitor and Transporter
Methods and Systems for Network Devices and Associated Network Transmissions
Patent:
9,590,897 →
Application:
14/632,200 →
Managing Reuse Information in Caches
Managing Reuse Information with Multiple Translation Stages
Communication and Control Topology for Efficient Testing of Sets of Devices
Design and Verification of a Multichip Coherence Protocol
Managing Address-Independent Page Attributes
Repeater Insertions Providing Reduced Routing Perturbation Caused by Flip-Flop Insertions
Phantom Queue Link Level Load Balancing System, Method and Device
Phantom Queue Link Level Load Balancing System, Method and Device
Phantom Queue Link Level Load Balancing System, Method and Device
Packet Processor Forwarding Database Cache
Testbench Builder, System, Device and Method Including Latency Detection
Software Assisted Hardware Configuration for Software Defined Network System-On-Chip
Method and Apparatus for Bypass Routing of Multicast Data Packets and Avoiding Replication to Reduce Overall Switch Latency
Testbench Builder, System, Device and Method with Phase Synchronization
Co-Verification - of Hardware and Software, a Unified Approach in Verification
Patent:
9,372,772 →
Application:
14/671,993 →
Packet Tracking in a Verification Environment
Packet Processing System, Method and Device Utilizing Memory Sharing
Control Path Subsystem, Method and Device Utilizing Memory Sharing
Datapath Subsystem, Method and Device Utilizing Memory Sharing
Packet Processing System, Method and Device Utilizing Memory Sharing
Packet Memory System, Method and Device for Preventing Underrun
Packet Processing System, Method and Device to Optimize Packet Buffer Space
Packet Processing System, Method and Device Having Reduced Static Power Consumption
Variable Strobe for Alignment of Partially Invisible Data Signals
Patent:
9,349,434 →
Application:
14/672,874 →
Determination of Flip-Flop Count in Physical Design
Compiler Architecture for Programmable Application Specific Integrated Circuit Based Network Devices
Compiler Architecture for Programmable Application Specific Integrated Circuit Based Network Devices
Code Generator for Programmable Network Devices
Algorithm to Achieve Optimal Layout of Instruction Tables for Programmable Network Devices
Algorithm to Derive Logic Expression to Select Execution Blocks for Programmable Network Devices
Identifying Inversion Error in Logic Equivalence Check
Algorithm to Achieve Optimal Layout of Decision Logic Elements for Programmable Network Devices
Method and Apparatus for Using Multiple Linked Memory Lists
Method and Apparatus for Using Multiple Linked Memory Lists
Approach for Logic Signal Grouping and Rtl Generation Using Xml
Approach for Chip-Level Flop Insertion and Verification Based on Logic Interface Definition
Parser Engine Programming Tool for Programmable Network Devices
Code Processor to Build Orthogonal Execution Blocks for Programmable Network Devices
Barrel Compactor System, Method and Device
Barrel Compactor System, Method and Device
Barrel Compactor System, Method and Device Having Cell Combination Logic
Policer Architecture
Packet Processing System, Method and Device Utilizing a Port Client Chain
Packet Processing System, Method and Device Utilizing a Port Client Chain
Packet Processing System, Method and Device Utilizing a Port Client Chain
Method and Apparatus for Handling Modified Constellation Mapping Using a Soft Demapper
Method and Apparatus for Discarding Unused Points from Constellation Mapping Rule Using Transceiver Processing Hardware ("Tph")
Methods and Systems for Control Block Routing
Patent:
9,720,733 →
Application:
14/698,581 →
Systems and Methods for Offloading Inline Ssl Processing to an Embedded Networking Device
Methods and Systems for Using Shared Logic at Network Devices
Patent:
9,588,839 →
Application:
14/805,161 →
Caching Methods and Systems Using a Network Interface Card
Systems and Methods for Offloading Ipsec Processing to an Embedded Networking Device
Method and Apparatus for Providing a Low Latency Transmission System Using Adaptive Buffering Estimation
Method and Apparatus for Providing a Low Latency Transmission System Using Adjustable Buffers
Method and Apparatus for Providing A Low Latency Transmission System Using Adaptive Buffering Estimation
Systems and Methods for Perfect Forward Secrecy (Pfs) Traffic Monitoring via a Hardware Security Module
Local Ordering of Instructions in a Computing System
Local Instruction Ordering Based on Memory Domains
Systems and Methods for Offloading Link Aggregation to a Host Bus Adapter (Hba) in Single Root I/O Virtualization (Sriov) Mode
Switching Methods and Systems for a Network Interface Card
Patent:
9,800,524 →
Application:
14/864,323 →
Input Output Value Prediction with Physical or Virtual Addressing for Virtual Environment
Methods and Systems for Managing Address List Control Blocks
Patent:
9,753,852 →
Application:
14/919,508 →
Systems and methods for dynamic regression test generation using coverage-based clustering
Methods and Systems for Processing Read and Write Requests
Patent:
9,946,671 →
Application:
14/969,950 →
Voltage-Controlled Oscillator with Improved Tuning Curve Linearization
Patent:
9,673,753 →
Application:
15/000,840 →
Method and Apparatus for Determining Metric for Selective Caching
Protocol Independent Programmable Switch (Pips) Software Defined Data Center Networks
Protocol Independent Programmable Switch (Pips) for Software Defined Data Center Networks
Managing Translation Invalidation
Managing Synonyms in Virtual-Address Caches
Method and Apparatus for Shared Multi-Port Memory Access
Application:
15/099,552 →
Publication:
US US20170301382A1
Method and Apparatus for Dynamic Virtual System on Chip
Voltage Regulator with Adaptive Bias Network
Edge Rate Control Calibration
Patent:
9,590,797 →
Application:
15/143,282 →
Systems and Methods for Text Analytics Processor
Systems and Methods for Deep Learning Processor
Systems and Methods for Virtio Based Optimization of Data Packet Paths Between a Virtual Machine and a Network Device for Live Virtual Machine Migration
Method and Apparatus for Efficient and Flexible Direct Memory Access
Process-Compensated Level-Up Shifter Circuit
Methods and Apparatus for Providing Soft and Blind Combining for Pusch Cqi Processing
Methods and Apparatus for Providing Soft and Blind Combining for PUSCH Acknowledgement (ACK) Processing
Methods and Apparatus for Providing Soft and Blind Combining for PUSCH Acknowledgement (ACK) Processing
Systems and Methods for Vectorized Fft for Multi-Dimensional Convolution Operations
Methods and Systems for Securing Data Stored at a Storage Area Network
Patent:
10,129,219 →
Application:
15/169,466 →
Managing Virtual-Address Caches for Multiple Memory Page Sizes
Admission Control for Memory Access Requests
Managing Memory Access Requests with Prefetch for Streams
Managing Memory Access Requests with Prefetch for Streams
Methods and Apparatus for Providing a Programmable Mixed-Radix DFT/IDFT Processor Using Vector Engines
Methods and Apparatus for a Vector Memory Subsystem for Use with a Programmable Mixed-Radix Dft/Idft Processor
Method and Apparatus for a Vector Memory Subsystem for Use with a Programmable Mixed-Radix Dft/Idft Processor
Methods and Apparatus for Twiddle Factor Generation for Use with a Programmable Mixed-Radix DFT/IDFT Processor
Methods and Apparatus for Twiddle Factor Generation for Use with A Programmable Mixed-Radix DFT/IDFT Processor
Phase Measurement and Correction Circuitry
Patent:
9,698,808 →
Application:
15/335,816 →
Methods and Systems for Message Logging and Retrieval in Computer Systems
Patent:
10,275,261 →
Application:
15/363,995 →
Methods and Apparatus for Providing an Fft Engine Using a Reconfigurable Single Delay Feedback Architecture
Methods and Apparatus for Configuring a Front End to Process Multiple Sectors with Multiple Radio Frequency Frames
Duty Cycle Correction Method
Methods and Apparatus for Control Bit Detection
Signal Presence Detection Circuit And Method
Frequency Divider
Method and Apparatus for Port Access Management at a Distributed Job Manager in a Digital Multi-Processor System
Methods and Apparatus for Frequency Offset Estimation
Methods and Apparatus for Frequency Offset Estimation
Methods And Apparatus For A Unified Baseband Architecture
Methods and Apparatus for Adaptive Power Profiling in a Baseband Processing System
Methods and Apparatus for Adaptive Power Profiling in A Baseband Processing System
Methods and Systems for Overlapping Protection Domain in Network Devices
Patent:
10,419,481 →
Application:
15/596,860 →
Method and Apparatus for Load Balancing of Jobs Scheduled for Processing
Multi-Phase Divider
Patent:
9,966,964 →
Application:
15/602,774 →
Flowlet Scheduler for Multicore Network Processors
Managing Lock and Unlock Operations Using Operation Prediction
Managing Lock and Unlock Operations Using Traffic Prioritization
Managing Fairness for Lock and Unlock Operations Using Operation Prioritization
Managing Lock and Unlock Operations Using Active Spinning
Timestamp-Based Packet Switching Using a Trie Data Structure
Managing Cache Partitions Based on Cache Usage Information
Methods and Systems for Data Alignment in Network Devices
Patent:
10,020,929 →
Application:
15/670,841 →
Method and Apparatus for Uplink Control Channel Detection
Method and Apparatus for Coordinated Multipoint Receiver Processing Acceleration and Latency Reduction
Method And Circuit For Low Voltage Current-Mode Bandgap
Patent:
10,222,817 →
Application:
15/721,236 →
Methods and Apparatus for Calculating Transport Block (TB) Cyclic Redundancy Check (CRC) Values
Methods and Apparatus for Control Channel Detection in an Uplink Shared Channel
Methods and Apparatus for Control Channel Detection in An Uplink Shared Channel
Baseline Wander Compensation
Serializer/Deserializer (SerDes) Lanes with Lane-by-Lane Datarate Independence
Multi-Termination Scheme Interface
Self-Biased Current Trimmer With Digital Scaling Input
Modular Serializer and Deserializer
Patent:
10,141,949 →
Application:
15/805,631 →
Method And Apparatus For Multi-Band Voltage-Controlled Oscillator (VCO) Band Selection
Issuing Instructions Based on Resource Conflict Constraints in Microporcessor
External Dqs Bi-Directional Loopback with Use of Feed Forward Equalization Path
Combined Conditional Branch and Indirect Branch Target Predictor
Complex I/O Value Prediction for Multiple Values with Physical or Virtual Addresses
Limiting Backpressure With Bad Actors
Method To Limit Packet Fetching With Uncertain Packet Sizes To Control Line Rate
System and Method For Performing a Failure Assessment of an Integrated Circuit
Application:
62/771,466 →
Write and Read Common Leveling for 4-Bit Wide Drams
Patent:
10,418,125 →
Application:
16/039,922 →
Write and Read Common Leveling for 4-Bit Wide Drams
Patent:
10,892,032 →
Application:
16/536,183 →
Merge Execution Unit for Microinstructions
Pair Merge Execution Units for Microinstructions
Voq-Based Network Switch Architecture Using Multi-Stage Arbitration Fabric Scheduler
Compressing Like Magnitude Partial Products in Multiply Accumulation
Method of Improving L1 Icache Performance with Large Programs
Methods and Systems for Distributing Memory Requests
Patent:
10,558,573 →
Application:
16/128,369 →
Low Latency Interconnect Protocol for Coherent Multi-Chip Communication
Flexible Resource Assignment to Physical and Virtual Functions in a Virtualized Processing System
Prefetching Data to Reduce Cache Misses
Increasing the Lookahead Amount for Prefetching
Secure Low-latency Chip-to-Chip Communication
Apparatus and Method for Scalable and Flexible Access Control List Lookup in a Network Switch
Apparatus and Method for Scalable and Flexible Table Search in a Network Switch
Apparatus and Method for Fast Search Table Update in a Network Switch
Reconfigurable Interconnect Element with Local Lookup Tables Shared by Multiple Packet Processing Engines
Method and Apparatus for Generating Parallel Lookup Requests Utilizing a Super Key
Apparatus and Method for Collecting Responses to a Plurality of Parallel Lookup Queries from a Flow of Packets at a Network Switch
Systems and Methods for Timing Adjustment of Metadata Paths in a Network Switch Under Timing Constraints
System and Method for Configuring a Plurality of Registers with Soft Error Detection and Low Wiring Complexity
Apparatus and Method for on-Chip Crossbar Design in a Network Switch Using Benes Network
Apparatus and Method for Parallel Crc Units for Variably-Sized Data Frames
Apparatus and Method for Optimized N-Write/1-Read Port Memory Design
Apparatus and Method for Enabling Flexible Key in a Network Switch
Apparatus and Method for Scalable and Flexible Wildcard Matching in a Network Switch
Programmable Hardware Scheduler for Digital Processing Systems
Method and Apparatus for Scheduling Arbitration Among a Plurality of Service Requestors
Method and Apparatus for Job Pre-Scheduling by Distributed Job Manager in a Digital Multi-Processor System
Re-Ordering Buffer for a Digital Multi-Processor System with Configurable, Scalable, Distributed Job Manager
Write and Read Common Leveling for 4-Bit Wide Drams
Patent:
10,497,413 →
Application:
16/040,249 →
Systems and Methods for Nvme Controller Virtualization to Support Multiple Virtual Machines Running on a Host
Packet Scheduling Using Hierarchical Scheduling Process with Priority Propagation
Secure Software and Hardware Association Technique
Secure Software and Hardware Association Technique
System and Method For Performing a Failure Assessment of an Integrated Circuit
Patent:
11,669,419 →
Application:
16/696,789 →
Display Panel and Terminal Device
Method and Apparatus for Providing a Low Latency Transmission System Using Adjustable Buffers
Direct Hardware Processing of Internal Data Structure Fields
Patent:
8,555,260 →
Application:
11/949,755 →
Memory Management in a Network Adapter
Patent:
8,619,558 →
Application:
12/176,750 →
Related Assignments
(20)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Jul 1, 2009
From: WAVESAT INC.
To: COMERICA BANK
Reel/Frame 022892/0829 →
Release
May 26, 2010
From: SILICON VALLEY BANK
To: CAVIUM NETWORKS INC
Reel/Frame 024445/0207 →
Termination Release and Discharge of Security Interest
May 10, 2011
From: WAVESAT, INC.
To: CAVIUM, INC.
Reel/Frame 026677/0299 →
Assignment of Assignor's Interest
Jun 1, 2011
From: WAVESAT, INC.
To: CAVIUM, INC.
Reel/Frame 026605/0828 →
Merger
Jul 18, 2011
From: CAVIUM NETWORKS, INC.
To: CAVIUM, INC.
Reel/Frame 026610/0478 →
Assignment of Assignor's Interest
May 20, 2015
From: MAHESHWARI, ASEEM; BERTONE, MICHAEL S.; KESSLER, RICHARD E.
To: CAVIUM, INC.
Reel/Frame 035679/0393 →
Assignment of Assignor's Interest
May 17, 2016
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: CAVIUM, INC.
Reel/Frame 038622/0066 →
Security Agreement
Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
Change of Name
Dec 14, 2016
From: QLOGIC SWITCH PRODUCTS, INC.
To: QLOGIC SWITCH PRODUCTS, LLC
Reel/Frame 040939/0819 →
Security Agreement
Mar 1, 2017
From: QLOGIC CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 041854/0119 →
Merger
Oct 18, 2017
From: QLOGIC CORPORATION
To: CAVIUM, INC.
Reel/Frame 044812/0504 →
Assignment of Assignor's Interest
Oct 20, 2017
From: QLOGIC SWITCH PRODUCTS, LLC
To: QLOGIC LLC
Reel/Frame 043912/0521 →
Change of Name
Nov 3, 2017
From: QLOGIC CORPORATION
To: QLOGIC LLC
Reel/Frame 044366/0832 →
Merger
Dec 14, 2017
From: QLOGIC CORPORATION
To: CAVIUM, INC.
Reel/Frame 045628/0419 →
Release of Security Interest
Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
Certificate of Conversion and Certificate of Formation
Oct 2, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047185/0422 →
Change of Name
Oct 8, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047205/0953 →
Change of Name
Jan 11, 2019
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 049367/0717 →
Assignment of Assignor's Interest
May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
Assignment of Assignor's Interest
Sep 24, 2020
From: QLOGIC LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 053874/0138 →