Apparatus and method for optimizing the number of accesses to page-reference count storage in page link list based switches
A packet processor includes a packet memory manager configured to receive a single header reference count and a single payload reference count for a packet. A page link list walk for the header under the control of the header reference count is performed in parallel with a page link list walk for the payload under the control of the payload reference count.
1. A packet processor, comprising:
a packet memory manager configured to
receive a single header reference count and a single payload reference count for a packet with a header and a payload; and
perform in parallel a page link list walk for the header under the control of the single header reference count and a page link list walk for the payload under the control of the single payload reference count, wherein each page link list walk traverses a linked list of all pages that a particular packet uses in packet memory.
2. The packet processor of claim 1 wherein the single header reference count is associated with a first header page for the packet.
3. The packet processor of claim 1 wherein the single payload reference count is associated with a first payload page for the packet.
4. The packet processor of claim 1 wherein the packet memory manager is configured to process a payload valid indication.
5. The packet processor of claim 1 wherein the packet memory manager is configured to free a page when the single payload reference count is one.
6. The packet processor of claim 1 wherein the packet memory manager is configured to free individual pages after a first reference page is recycled.
7. The packet processor of claim 1 further comprising:
a packet memory manager configured to
receive an indicator of reference count invalidity; and
free a header page and a payload page in response to the indication of reference count invalidity without accessing a reference count.