Patent Assignment
Reel/Frame 039715/0449
Security Agreement
Recorded: 2016-08-17
Pages: 31
Assignee
JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
10 S. DEARBORN, FLOOR L-2, CB COLLATERAL SERVICES, CHICAGO, ILLINOIS, 60603
Covered Properties
(420)
Ofdm Receiving System
Patent:
6,151,295 →
Application:
09/030,865 →
Random Number Generator
Patent:
6,954,770 →
Application:
09/938,166 →
Method and Apparatus for Establishing Secure Sessions
Interface for a Security Coprocessor
Patent:
6,789,147 →
Application:
10/025,512 →
Method and Apparatus to Implement the Data Encryption Standard Algorithm
Patent:
7,076,059 →
Application:
10/052,054 →
Method and Apparatus for Montgomery Multiplication
Patent:
7,035,889 →
Application:
10/068,677 →
On-Chip Inter-Subsystem Communication
Speculative Execution for Data Ciphering Operations
Patent:
7,260,217 →
Application:
10/092,328 →
Decoupled Architecture for Data Ciphering Operations
Patent:
7,305,567 →
Application:
10/234,895 →
Apparatus and Method for Repairing Logic Blocks
Patent:
6,861,865 →
Application:
10/387,151 →
Apparatus and Method for Data Deskew
Patent:
7,209,531 →
Application:
10/397,083 →
Transparent Ipsec Processing Inline Between a Framer and a Network Component
Apparatus and Method for Allocating Resources Within a Security Processing Architecture Using Multiple Groups
Apparatus and Method for Allocating Resources Within a Security Processing Architecture Using Multiple Queuing Mechanisms
Apparatus and Method for Allocating Resources Within a Security Processor
Ipsec Performance Optimization
Security System with an Intelligent Dma Controller
Subsystem Boot and Peripheral Data Transfer Architecture for a Subsystem of a System-on- Chip
Synchronizing Method and Apparatus
Mosfet-Fused Nonvolatile Read-Only Memory Cell (Mofrom)
Patent:
6,949,423 →
Application:
10/723,004 →
Store Instruction Ordering for Multi-Core Processor
Packet Queuing, Scheduling and Ordering
Local Scratchpad and Data Caching System
Direct Access to Low-Latency Memory
Apparatus and Method for Repairing Logic Blocks
Patent:
7,205,785 →
Application:
11/040,266 →
Tcp Engine
Deterministic Finite Automata (Dfa) Instruction
Deterministic Finite Automata (Dfa) Processing
Content Search Mechanism That Uses a Deterministic Finite Automata (Dfa) Graph, a Dfa State Machine, and a Walker Process
Method and Apparatus for Reducing Host Overhead in a Socket Server Implementation
Selective Replication of Data Structures
Method and System for Motion Estimation with Multiple Vector Candidates
On-Chip Inter-Subsystem Communication
Congestion Reducing Reliable Transport Packet Retry Engine
Resistively Loaded Single Stage Differential Amplifier Having Zero Volt Common Mode Input
Graph Caching
Intelligent Graph Walking
Deterministic Finite Automata (Dfa) Graph Compression
Method and Apparatus for Traversing a Compressed Deterministic Finite Automata (Dfa) Graph
Method and System for Selection of Reference Picture and Mode Decision
Single-Ended to Differential Converter
Method and Apparatus for Content Based Searching
Deterministic Finite Automata Graph Traversal with Nodal Bit Mapping
Multiple core Session Initiation Protocol (SIP)
Secure Software and Hardware Association Technique
Profile-Based and Dictionary Based Graph Caching
Application:
12/505,324 →
Publication:
US 2011/0016154
Method and Apparatus for Reducing Host Overhead in a Socket Server Implementation
Dll-Based Temperature Sensor
Method and Apparatus for Correcting Linear Error Phase of an Ofdm Signal
Method and Apparatus for Estimating Overshoot Power After Estimating Power of Executing Events
Method and Apparatus for a Virtual System on Chip
System and Method for Low-Latency Multimedia Streaming
System and Method for Enabling Access to a Protected Hardware Resource
System and Method for Optimizing Use of Channel State Information
On-Demand Intra-Refresh for End-to End Coded Video Transmission Systems
Low latency rate control system and method
Video encoder bit estimator for macroblock encoding
System and Method of Compression and Decompression
System and Method for Secure Device Key Storage
Compression with Adjustable Quality/Bandwidth Capability
Anchored Patterns
Regular Expression Processing Automaton
Regex Compiler
Secure Software and Hardware Association Technique
Processor with Dedicated Virtual Functions and Dynamic Assignment of Functional Resources
Qos Based Dynamic Execution Engine Selection
Processor With Efficient Work Queuing
Packet Priority in a Network Processor
System and Method to Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports
System and Method to Provide Non-Coherent Access to a Coherent Memory System
Input Output Bridging
Multi-Protocol Serdes Phy Apparatus
Word Boundary Lock
Bit Error Rate Impact Reduction
Packet Traffic Control in a Network Processor
Network Processor with Distributed Trace Buffers
Multi-Core Interconnect in a Network Processor
Work Request Processor
Reverse Nfa Generation and Processing
Graph Caching
Dram Address Protection
Messaging with Flexible Transmit Ordering
Differential Amplifier with Duty Cycle Compensation
State Machine for Deskew Delay Locked Loop
Level-Up Shifter Circuit
Multi-Function Delay Locked Loop
Memory Interface with Selectable Evaluation Modes
Synchronized Clock Phase Interpolator
Differential Amplifier with De-Emphasis
High Speed Variable Bandwidth Ring-Based System
System and Method for Storing Lookup Request Rules in Multiple Memories
Method and Apparatus Encoding a Rule for a Lookup Request in a Processor
System and Method for Rule Matching in a Processor
Lookup Cluster Complex
Work Migration in a Processor
Lookup Front End Packet Input Processor
Method and Apparatus for Multiple Access of Plural Memory Banks
On-Chip Memory (Ocm) Physical Bank Parallelism
Method and Apparatus for Managing Transport Operations to a Cluster Within a Processor
Method and Apparatus for Managing Transfer of Transport Operations from a Cluster in a Processor
Method and Apparatus for Assigning Resources Used to Manage Transport Operations Between Clusters Within a Processor
Method and Apparatus for Managing Processing Thread Migration Between Clusters Within a Processor
Lookup Front End Packet Output Processor
Incremental Update
Packet Classification
Lookup Front End Packet Input Processor
Identifying Duplication in Decision Trees
Decision Tree Level Merging
Method and Apparatus for Power Control
Apparatus and Method for Media Access Control Scheduling with a Sort Hardware Coprocessor
Apparatus and Method for Media Access Control Scheduling with a Priority Calculation Hardware Coprocessor
Incremental Update Heuristics
Rule Modification in Decision Trees
Batch Incremental Update
Duplication in Decision Trees
Scope in Decision Trees
Patent:
9,195,939 →
Application:
13/840,867 →
Multi-Host Processing
Patent:
9,531,647 →
Application:
13/841,743 →
Packet Extraction Optimization in a Network Processor
Phased Bucket Pre-Fetch in a Network Processor
Method and Apparatus for Data Packet Integrity Checking in a Processor
Method and Apparatus for Scheduling Rule Matching in a Processor
Method and an Accumulator Scoreboard for Out-of-Order Rule Response Handling
System And Method Of Compression And Decompression
Compiler with Mask Nodes
Patent:
9,595,003 →
Application:
13/896,798 →
Lookup Cluster Complex
Deterministic Finite Automata Graph Traversal With Nodal Bit Mapping
Input Output Bridging
Apparatus and Method for Uniquely Enumerating Paths in a Parse Tree
Application:
13/921,090 →
Publication:
US 2014/0369363
Level-Up Shifter Circuit for High Speed and Low Power Applications
Method and Apparatus for Compilation of Finite Automata
Clock Gated Delay Line Based On Setting Value
Clock Distribution Circuit with Distributed Delay Locked Loop
Method and Apparatus for Processing Finite Automata
System And Method To Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports
Messaging with Flexible Transmit Ordering
Memory Interface With Integrated Tester
Merged TLB Structure For Multiple Sequential Address Translations
Collapsed Address Translation With Multiple Page Sizes
Maintenance Of Cache And Tags In A Translation Lookaside Buffer
Translation Bypass In Multi-Stage Address Translation
Method and Apparatus for Managing Global Chip Power on a Multicore System on Chip
Auto-Blow Memory Repair
Content Search Mechanism That Uses A Deterministic Finite Automata (DFA) Graph, A DFA State Machine, And A Walker Process
Dynamically Adjusting Supply Voltage Based On Monitored Chip Temperature
Method and Apparatus for Reference Voltage Calibration in a Single-Ended Receiver
Method and Apparatus for Amplifier Offset Calibration
Method and Apparatus for Calibrating an Input Interface
Clock Multiplexing and Repeater Network
Protocol Switching over Multi-Network Interface
Method And Apparatus For Supporting Wide Operations Using Atomic Sequences
Data Strobe Generation
Method And Apparatus For Conditional Storing Of Data Using A Compare-And-Swap Based Approach
Method and Apparatus for Aligning Signals
Multiple Core Session Initiation Protocol (SIP)
Application:
14/067,524 →
Publication:
US 2014/0059241
Method and Apparatus to Represent a Processor Context with Fewer Bits
Lookup Front End Packet Output Processor
Virtualized Network Interface for Tcp Reassembly Buffer Allocation
Virtualized Network Interface for Lockdown and Overlay of Data in Transmitted Packets
Virtualized Network Interface for Remote Direct Memory Access Over Converged Ethernet
Lookup Front End Packet Input Processor
System and a Method for a Remote Direct Memory Access Over Converged Ethernet
Method and an Apparatus for Memory Address Allignment
Method and an Apparatus for Virtualization of a Quality-Of-Service
Method and an Apparatus for Converting Interrupts into Scheduled Events
System for and Method of Combining Cmos Inverters of Multiple Drive Strengths to Create Tune-Able Clock Inverters of Variable Drive Strengths in Hybrid Tree-Mesh Clock Distribution Networks
System for and Method of Placing Clock Stations Using Variable Drive-Strength Clock Drivers Built Out of a Smaller Subset of Base Cells for Hybrid Tree-Mesh Clock Distribution Networks
System for and Method of Tuning Clock Networks Constructed Using Variable Drive-Strength Clock Inverters with Variable Drive-Strength Clock Drivers Built Out of a Smaller Subset of Base Cells
Apparatus and Method for Interrupt Collecting and Reporting Status and Delivery Information
Look-Aside Processor Unit with Internal and External Access for Multicore Processors
Matrix of on-Chip Routers Interconnecting a Plurality of Processing Engines and a Method of Routing Using Thereof
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Apparatus and Method for Packet Memory Datapath Processing in High Bandwidth Packet Processing Devices
Patent:
9,256,380 →
Application:
14/142,612 →
Apparatus and Method for Time Stamping Packets Across Several Nodes in a Network
Patent:
9,509,585 →
Application:
14/142,623 →
Apparatus and Method for Optimizing the Number of Accesses to Page-Reference Count Storage In Page Link List Based Switches
Patent:
9,438,539 →
Application:
14/142,631 →
Apparatus and Method for Accelerated Page Link List Processing in a Packet Processor Operating at Wirespeed
Patent:
9,009,364 →
Application:
14/142,643 →
Method for Storing and Retrieving Packets in High Bandwidth and Low Latency Packet Processing Devices
Patent:
9,736,069 →
Application:
14/142,653 →
Method and Apparatus for Processing of Finite Automata
System and Method for Optimizing Use of Channel State Information
Method and Apparatus for Parallel and Conditional Data Manipulation in a Software-Defined Network Processing Engine
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Method and System for Skipping Over Group(S) of Rules Based on Skip Group Rule
Multi-Rule Approach to Encoding a Group of Rules
Processing Request Keys Based on a Key Size Supported by Underlying Processing Elements
Method and Apparatus for Compiling Search Trees for Processing Request Keys Based on a Key Size Supported by Underlying Processing Elements
Methods and Systems for Single Instruction Multiple Data Programmable Packet Parsers
Application:
14/150,602 →
Publication:
US 2015/0195383
Packet Parsing Engine
Methods and Systems for Distribution of Packets Among Parsing Clusters
Methods and Systems for Resource Management in a Single Instruction Multiple Data Packet Parsing Cluster
Methods and Systems for Flexible Packet Classification
Application:
14/150,657 →
Publication:
US 2015/0195387
Floating Mask Generation for Network Packet Flow
Condition Code Approach for Comparing Rule and Packet Data That Are Provided in Portions
Systems and Methods for Specifying. Modeling, Implementing and Verifying Ic Design Protocols
Block Mask Register Key Processing by Compiling Data Structures to Traverse Rules and Creating a New Rule Set
Method and Apparatus for Managing Write Back Cache
Method And Apparatus For Optimizing Finite Automata Processing
Finite Automata Processing Based on a Top of Stack (TOS) Memory
Method and an Apparatus for Work Packet Queuing, Scheduling, and Ordering with Conflict Queuing
Application:
14/170,955 →
Publication:
US 2015/0220872
Method and an Apparatus for Work Request Arbitration in a Network Processor
Method and an Apparatus for Pre-Fetching and Processing Work for Procesor Cores in a Network Processor
Multiple Ethernet Ports and Port Types Using a Shared Data Path
System and Method to Traverse a Non-Deterministic Finite Automata (NFA) Graph Generated for Regular Expression Patterns with Advanced Features
Generating a Non-Deterministic Finite Automata (NFA) Graph for Regular Expression Patterns with Advanced Features
Method and Apparatus for Memory Access Management
Cdr Voter with Improved Frequency Offset Tolerance
Partitioned Error Code Computation
Packet Output Processing
Method And Apparatus For Power Gating Hardware Components In A Chip Device
Packet Scheduling in a Network Processor
Packet Shaping in a Network Processor
System on Chip Link Layer Protocol
Apparatus and Method for Processing Alternately Configured Longest Prefix Match Tables
Scannable Flop with a Single Storage Element
Multi-Core Network Processor Interconnect with Multi-Node Connection
Application:
14/201,507 →
Publication:
US 2015/0254182
Inter-Chip Interconnect Protocol for a Multi-Chip System
Method and System for Work Scheduling in a Multi-Chip System
Method and System for Ordering I/O Access in a Multi-Node Environment
Method and Apparatus for Memory Allocation in a Multi-Node System
Apparatus and Method for Table Search with Centralized Memory Pool in a Network Switch
Method and Apparatus for Low Latency Exchange of Data Between a Processor and Coprocessor
Application:
14/204,374 →
Publication:
US 2015/0261535
Merging Independent Writes, Separating Dependent And Independent Writes, And Error Roll Back
NSP Manager
Multiplexer Flop
Work Migration in a Processor
Compilation of Finite Automata Based on Memory Hierarchy
Processing Of Finite Automata Based On Memory Hierarchy
Memory Management for Finite Automata Processing
Processing of Finite Automata Based on a Node Cache
Systems and Methods for Nvme Controller Virtualization to Support Multiple Virtual Machines Running on a Host
System and Method for Automated Functional Coverage Generation and Management for Ic Design Protocols
Method and Apparatus for Analytics in a Network Switch
Method and Apparatus for Table Aging in a Network Switch
Systems and Methods for Cloud-Based Web Service Security Management Basedon Hardware Security Module
Application:
14/299,739 →
Publication:
US 2016/0149877
Systems and Methods for Enabling Access to Extensible Storage Devices Over a Network as Local Storage via Nvme Controller
Counter with Overflow Fifo and a Method Thereof
Application:
14/302,343 →
Publication:
US 2015/0365339
Hierarchical Statistically Multiplexed Counters and a Method Therof
Method of Modifying Packets to a Generic Format for Enabling Programmable Modifications and an Apparatus Thereof
Method of Representing a Generic Format Header Using Continuous Bytes and an Apparatus Thereof
Method of Using a Unique Packet Identifier to Identify Structure of a Packet and an Apparatus Thereof
Method of Using Generic Modification Instructions to Enable Flexible Modifications of Packets and an Apparatus Thereof
Method of Using Bit Vectors to Allow Expansion and Collapse of Header Layers Within Packets for Enabling Flexible Modifications and an Apparatus Thereof
Method of Splitting a Packet into Individual Layers for Modification and Intelligently Stitching Layers Back Together After Modification and an Apparatus Thereof
Leaky Bucket Model to Mimic Behavior of a Mac and a Method Thereof
Application:
14/309,700 →
Publication:
US 2015/0372926
Method of Extracting Data from Packets and an Apparatus Thereof
Method of Forming a Hash Input from Packet Contents and an Apparatus Thereof
Method of Handling Large Protocol Layers for Configurable Extraction of Layer Information and an Apparatus Thereof
Method of Reducing Latency in a Flexible Parser and an Apparatus Thereof
Method of Dynamically Renumbering Ports and an Apparatus Thereof
Method of Identifying Internal Destinations of Network Packets and an Apparatus Thereof
Systems and Methods for Enabling Local Caching for Remote Storage Devices Over a Network via Nvme Controller
Application:
14/317,467 →
Publication:
US 2015/0317091
Intelligent Graph Walking
Application:
14/324,682 →
Publication:
US 2014/0324900
Engine Architecture for Processing Finite Automata
Managing Instruction Order in a Processor Pipeline
Application:
14/328,923 →
Publication:
US 2016/0011877
Managing Instruction Order in a Processor Pipeline
Application:
14/328,951 →
Publication:
US 2016/0011876
Video Encoder Bit Estimator for Macroblock Encoding
Network Device, System and Method Having a Rotated Chip Floorplan
Application:
14/331,099 →
Publication:
US 2016/0014885
Baseboard Interconnection Device, System and Method
Content Search Mechanism That Uses A Deterministic Finite Automata (DFA) Graph, A DFA State Machine, And A Walker Process
Secure Software and Hardware Association Technique
Method and an Apparatus for Co-Processor Data Plane Virtualization
Method and Apparatus for a Virtual System on Chip
Method and Apparatus for a Virtual System on Chip
System and Method to Provide Non-Coherent Access to a Coherent Memory System
Systems and Methods for Enabling Value Added Services for Extensible Storage Devices Over a Network via Nvme Controller
Application:
14/473,111 →
Publication:
US 2015/0317176
Low Latency Rate Control System and Method
Method And Apparatus For Power Control
Word Boundary Lock
Method and Apparatus for Improving Data Integrity Using Compressed Soft Information
Method and Apparatus for Quantizing Soft Information Using Non-Linear LLR Quantization
Method and Apparatus for Quantizing Soft Information Using Linear Quantization
Hierarchical Hardware Linked List Approach for Multicast Replication Engine in a Network Asic
Fast Hardware Switchover in a Control Path in a Network Asic
Session Based Packet Mirroring in a Network Asic
Multicast Replication Engine of a Network Asic and Methods Thereof
Flexible Instruction Execution in a Processor Pipeline
Flexible Instruction Execution in a Processor Pipeline
Traversal With Arc Configuration Information
Apparatus and a Method of Detecting Errors on Registers
Two Modes of a Configuration Interface of a Network Asic
Smart Holding Registers to Enable Multiple Register Accesses
Multiple-Interrupt Propagation Scheme in a Network Asic
Hybrid Wildcard Match Table
Systems and Methods for Supporting Migration of Virtual Machines Accessing Remote Storage Devices Over Network via Nvme Controllers
Adder Decoder
Programmable Validation of Transaction Requests
Programmable Ordering and Prefetch
Register Access Control Among Multiple Devices
Arbitrated Access To Resources Among Multiple Devices
Independent Ordering Of Independent Transactions
Application:
14/540,656 →
Publication:
US 2016/0139806
Apparatus and Method for Scalable and Flexible Table Search in a Network Switch
Apparatus and Method for Fast Search Table Update in a Network Switch
Translation Lookaside Buffer Management
Caching Tlb Translations Using a Unified Page Table Walker Cache
Distributed Interrupt Scheme in a Multi-Processor System
Translation Lookaside Buffer Invalidation Suppression
Distributed Timer Subsystem
Filtering Translation Lookaside Buffer Invalidations
Instruction Cache Translation Management
Application:
14/541,826 →
Publication:
US 2016/0140042
Apparatus and Method for Distributed Instruction Trace in a Processor System
Managing History Information for Branch Prediction
Managing Buffered Communication Between Sockets
Bypass Fifo for Multiple Virtual Channels
Managing Skew in Data Signals
Debug Interface for Multiple Cpu Cores
Testing Semiconductor Devices
Frequency Division Clock Alignment
Controlled Multi-Step De-Alignment of Clocks
Distributed Timer Subsystem Across Multiple Devices
Managing Buffered Communication Between Cores
Instruction Ordering for in-Progress Operations
Controlled Dynamic De-Alignment of Clocks
Managing Skew in Data Signals with Multiple Modes
Frequency Division Clock Alignment Using Pattern Selection
Method and Apparatus for Performing a Weighted Queue Scheduling Using a Set of Fairness Factors
Packet Scheduling Using Hierarchical Scheduling Process
Apparatus and Method for a Multi-Entity Secure Software Transfer
Packet Scheduling Using Hierarchical Scheduling Process with Priority Propagation
Network Switching with Co-Resident Data-Plane and Network Interface Controllers
Management of an Over-Subscribed Shared Buffer
Method and System for Improved Load Balancing of Received Network Traffic
Packet Classification
Network Switching with Layer 2 Switch Coupled Co-Resident Data-Plane and Network Interface Controllers
Phased Bucket Pre-Fetch in a Network Processor
Method And Apparatus For Managing Processing Thread Migration Between Clusters Within A Processor
On-Chip Memory (OCM) Physical Bank Parallelism
Application:
14/604,975 →
Publication:
US 2015/0143060
Method to Measure Edge-Rate Timing Penalty of Digital Integrated Circuits
High Performance Shifter Circuit
Testbench Builder, System, Device and Method Including a Generic Driver and Transporter
Application:
14/617,522 →
Publication:
US 2016/0139204
Testbench Builder, System, Device and Method
Testbench Builder, System, Device and Method Including a Dispatcher
Testbench Builder, System, Device and Method Including a Generic Monitor and Transporter
Testbench Builder, System, Device and Method Having Agent Loopback Functionality
Dram Address Protection
Apparatus and Method for Software Enabled Access to Protected Hardware Resources
Anchored Patterns
Automated Flip-Flop Insertions in Physical Design Without Perturbation of Routing
Communication and Control Topology for Efficient Testing of Sets of Devices
Managing Reuse Information for Memory Pages
Application:
14/637,579 →
Publication:
US 2016/0259732
Managing Reuse Information with Multiple Translation Stages
Managing Reuse Information in Caches
Multi-Function Delay Locked Loop
Lookup Cluster Complex
Systems and Methods for Secured Hardware Security Module Communication with Web Service Hosts
Application:
14/662,012 →
Publication:
US 2015/0358294
Managing Address-Independent Page Attributes
Repeater Insertions Providing Reduced Routing Perturbation Caused by Flip-Flop Insertions
Systems and Methods for Secured Key Management via Hardware Security Module for Cloud-Based Web Services
Application:
14/667,238 →
Publication:
US 2015/0358311
Packet Processor Forwarding Database Cache
Phantom Queue Link Level Load Balancing System, Method and Device
Work Request Processor
Method and Apparatus for Bypass Routing of Multicast Data Packets and Avoiding Replication to Reduce Overall Switch Latency
Testbench Builder, System, Device and Method with Phase Synchronization
Co-Verification - of Hardware and Software, a Unified Approach in Verification
Patent:
9,372,772 →
Application:
14/671,993 →
Software Assisted Hardware Configuration for Software Defined Network System-On-Chip
Packet Tracking in a Verification Environment
Testbench Builder, System, Device and Method Including Latency Detection
Managing Skew in Data Signals with Adjustable Strobe
Variable Strobe for Alignment of Partially Invisible Data Signals
Patent:
9,349,434 →
Application:
14/672,874 →
Packet Memory System, Method and Device for Preventing Underrun
Packet Processing System, Method and Device to Optimize Packet Buffer Space
Packet Processing System, Method and Device Having Reduced Static Power Consumption
Packet Processing System, Method and Device Utilizing a Port Client Chain
Packet Processing System, Method and Device Utilizing Memory Sharing
Control Path Subsystem, Method and Device Utilizing Memory Sharing
Datapath Subsystem, Method and Device Utilizing Memory Sharing
Identifying Inversion Error in Logic Equivalence Check
Approach for Chip-Level Flop Insertion and Verification Based on Logic Interface Definition
Determination of Flip-Flop Count in Physical Design
Approach for Logic Signal Grouping and Rtl Generation Using Xml
Method and Apparatus for Using Multiple Linked Memory Lists
Parser Engine Programming Tool for Programmable Network Devices
Code Processor to Build Orthogonal Execution Blocks for Programmable Network Devices
Algorithm to Achieve Optimal Layout of Decision Logic Elements for Programmable Network Devices
Algorithm to Derive Logic Expression to Select Execution Blocks for Programmable Network Devices
Algorithm to Achieve Optimal Layout of Instruction Tables for Programmable Network Devices
Code Generator for Programmable Network Devices
Compiler Architecture for Programmable Application Specific Integrated Circuit Based Network Devices
Barrel Compactor System, Method and Device
Barrel Compactor System, Method and Device Having Cell Combination Logic
Policer Architecture
Apparatus and Method for Accelerated Page Link List Processing in a Packet Processor Operating at Wirespeed
Patent:
9,262,369 →
Application:
14/676,791 →
Systems and Methods for Hardware Accelerated Timer Implementation for Openflow Protocol
Systems and Methods for Secured Backup of Hardware Security Modules for Cloud-Based Web Services
Messaging with Flexible Transmit Ordering
Qos Based Dynamic Execution Engine Selection
Systems and Methods for Secured Communication Hardware Security Module and Network-Enabled Devices
Application:
14/829,233 →
Publication:
US 2015/0358313
Method and Apparatus for Providing a Low Latency Transmission System Using Adjustable Buffers
Local Ordering of Instructions in a Computing System
Reverse Nfa Generation and Processing
Reverse NFA Generation And Processing
Application:
14/863,816 →
Publication:
US 2016/0021123
Systems and Methods for Allowing Flexible Chip Configuration by External Entity While Maintaining Secured Boot Environment
Scope In Decision Trees
Hybrid Wildcard Match Table
Systems and Methods for Hardware Accelerated Metering for Openflow Protocol
Carry Chain for Simd Operations
Implementing 128-Bit Simd Operations on a 64-Bit Datapath
Method and System for Compressing Data for a Translation Look Aside Buffer (Tlb)
Automatic Data Rate Matching
Approach for Interfacing a Pipeline with Two or More Interfaces in a Processor
Distributing Resource Requests in a Computing System
Sharing Resources in a Multi-Context Computing System
Systems and Methods for Enabling Local Caching for Remote Storage Devices Over a Network via Nvme Controller
Application:
14/941,396 →
Publication:
US 2016/0077740
Voltage-Controlled Oscillator with Improved Tuning Curve Linearization
Patent:
9,673,753 →
Application:
15/000,840 →
Protocol Independent Programmable Switch (Pips) Software Defined Data Center Networks
Managing Translation Invalidation
Managing Synonyms in Virtual-Address Caches
Content Search Pattern Matching Using Deterministic Finite Automata (Dfa) Graphs
Method and Apparatus for Dynamic Virtual System on Chip
Apparatus and Method for Processing Alternately Configured Longest Prefix Match Tables
Edge Rate Control Calibration
Patent:
9,590,797 →
Application:
15/143,282 →
Voltage Regulator with Adaptive Bias Network
System and Method for Rule Matching in a Processor
Methods and Apparatus for Providing Soft and Blind Combining for Pusch Cqi Processing
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Managing Virtual-Address Caches for Multiple Memory Page Sizes
Method and Apparatus for Providing Soft and Blind Combining Techniques for PUSCH Baseband Processing
Application:
62/267,221 →
Method and Apparatus for Providing Programmable Mixed-Radix Dft Processor Using Vector Engines
Application:
62/274,062 →
Method and Apparatus for Dynamically Generating Mixed-Radix Twiddle Coefficient Vectors
Application:
62/274,686 →
Method and Apparatus for Configuring Multiple Sectors with Multiple Radio Frequency Frames
Application:
62/274,709 →
Method and Apparatus for Providing Programmable Mixed-Radix DFT/IDFT Processor Using Vector Memory Subsystem
Application:
62/279,345 →
Method and Apparatus for Providing Fft Engine Using Single Delay Feedback Scheme
Application:
62/288,382 →
Frequency Offset Estimator
Application:
62/335,366 →
Related Assignments
(8)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name
Jun 19, 2012
From: CAVIUM NETWORKS, INC.
To: CAVIUM, INC.
Reel/Frame 028401/0382 →
Release of Security Interest
Jan 26, 2017
From: VENTURE LENDING & LEASING IV, INC.
To: CELESTIAL SEMICONDUCTOR, LTD
Reel/Frame 041513/0188 →
Release of Security Interest
Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
Certificate of Conversion and Certificate of Formation
Oct 2, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047185/0422 →
Change of Name
Jan 11, 2019
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 049367/0717 →
Assignment of Assignor's Interest
Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
Assignment of Assignor's Interest
May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
Change of Name
Jul 31, 2020
From: WAVESAT WIRELESS INC.
To: WAVESAT INC.
Reel/Frame 053376/0469 →