Multi-function delay locked loop
View Patent ↗A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.
1. A delay circuit comprising:
a delay line configured to receive a clock signal and output a delayed clock signal;
a delay controller configured to control the delay line to output the delayed clock signal at a quadrature delay relative to the clock signal;
a multiplexer receiving a plurality of delay signals, the delay signals including the clock signal and the delayed clock signals; and
a state machine configured to control the multiplexer to select one of the delay signals to provide write leveling among a plurality of associated output signals.
2. The delay circuit of claim 1 , wherein the delay signals further include complements of the clock signal and the delayed clock signal.
3. The delay circuit of claim 1 , further comprising a second delay line configured to receive a data strobe signal and output a delayed data strobe signal.
4. The delay circuit of claim 3 , wherein the state machine is further configured to control the multiplexer to select one of the delay signals to enable the data strobe signal at the second delay line.
5. The delay circuit of claim 3 , wherein the delay line and the second delay line are coupled during an idle period of the memory interface, the delay controller adjusting the quadrature delay of at least one of the delay line and the second delay line during the idle period.
6. The delay circuit of claim 3 , wherein the delay controller further includes at least two offset adders and subtractors, each of the offset adders and subtractors associated with a respective one of the delay line and the second delay line, the offset adders and subtractors being adjustable via a signal external to the delay circuit.
7. The delay circuit of claim 6 , wherein the at least two adders and subtractors are configured to generate an offset to the quadrature delay.
8. An interface circuit comprising:
a plurality of blocks, each block receiving a clock signal and a respective outbound data signal, each block comprising:
a delay line configured to receive the clock signal and output a delayed clock signal;
a delay controller configured to control the delay line to output the delayed clock signal at a quadrature delay relative to the clock signal;
a multiplexer receiving a plurality of delay signals, the delay signals including the clock signal and the delayed clock signals;
at least one flip-flop configured to receive the respective outbound data signal, the at least one flip-flop being clocked by the multiplexer output; and
a state machine configured to control the multiplexer at each of the blocks to select a delay signal to provide signal leveling among the respective outbound data signals.
9. The interface circuit of claim 8 , wherein the state machine is further configured to control the multiplexer to select one of the delay signals to provide read leveling among a plurality of associated input signals.
10. The delay circuit of claim 1 , wherein the state machine is further configured to control the multiplexer to select one of the delay signals to provide read leveling among a plurality of associated input signals.