Patent Assignment
Reel/Frame 047185/0422
Certificate of Conversion and Certificate of Formation
Recorded: 2018-10-02
Pages: 13
Assignor
CAVIUM, INC.
Executed: 2018-09-21
Assignee
CAVIUM, LLC
5488 MARVELL LANE, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(210)
Ipsec Performance Enhancement Using a Hardware-Based Parallel Process
Patent:
6,708,218 →
Application:
09/587,689 →
On-Chip Inter-Subsystem Communication
Security System with an Intelligent Dma Controller
Subsystem Boot and Peripheral Data Transfer Architecture for a Subsystem of a System-on- Chip
Store Instruction Ordering for Multi-Core Processor
Packet Queuing, Scheduling and Ordering
Local Scratchpad and Data Caching System
Direct Access to Low-Latency Memory
Tcp Engine
Deterministic Finite Automata (Dfa) Instruction
Deterministic Finite Automata (Dfa) Processing
Content Search Mechanism That Uses a Deterministic Finite Automata (Dfa) Graph, a Dfa State Machine, and a Walker Process
Method and Apparatus for Reducing Host Overhead in a Socket Server Implementation
Selective Replication of Data Structures
On-Chip Inter-Subsystem Communication
Congestion Reducing Reliable Transport Packet Retry Engine
Resistively Loaded Single Stage Differential Amplifier Having Zero Volt Common Mode Input
Graph Caching
Intelligent Graph Walking
Deterministic Finite Automata (Dfa) Graph Compression
Method and Apparatus for Traversing a Compressed Deterministic Finite Automata (Dfa) Graph
Single-Ended to Differential Converter
Method and Apparatus for Content Based Searching
Deterministic Finite Automata Graph Traversal with Nodal Bit Mapping
Multiple core Session Initiation Protocol (SIP)
Secure Software and Hardware Association Technique
Method and Apparatus for Reducing Host Overhead in a Socket Server Implementation
Dll-Based Temperature Sensor
Method and Apparatus for Estimating Overshoot Power After Estimating Power of Executing Events
Method and Apparatus for a Virtual System on Chip
System and Method of Compression and Decompression
Compression with Adjustable Quality/Bandwidth Capability
Anchored Patterns
Regular Expression Processing Automaton
Regex Compiler
Secure Software and Hardware Association Technique
Processor with Dedicated Virtual Functions and Dynamic Assignment of Functional Resources
Qos Based Dynamic Execution Engine Selection
Processor With Efficient Work Queuing
Packet Priority in a Network Processor
System and Method to Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports
System and Method to Provide Non-Coherent Access to a Coherent Memory System
Input Output Bridging
Multi-Protocol Serdes Phy Apparatus
Word Boundary Lock
Bit Error Rate Impact Reduction
Packet Traffic Control in a Network Processor
Network Processor with Distributed Trace Buffers
Multi-Core Interconnect in a Network Processor
Work Request Processor
Reverse Nfa Generation and Processing
Graph Caching
Dram Address Protection
Messaging with Flexible Transmit Ordering
Differential Amplifier with Duty Cycle Compensation
State Machine for Deskew Delay Locked Loop
Level-Up Shifter Circuit
Multi-Function Delay Locked Loop
Memory Interface with Selectable Evaluation Modes
Synchronized Clock Phase Interpolator
Differential Amplifier with De-Emphasis
High Speed Variable Bandwidth Ring-Based System
System and Method for Storing Lookup Request Rules in Multiple Memories
Method and Apparatus Encoding a Rule for a Lookup Request in a Processor
System and Method for Rule Matching in a Processor
Lookup Cluster Complex
Work Migration in a Processor
Lookup Front End Packet Input Processor
Method and Apparatus for Multiple Access of Plural Memory Banks
On-Chip Memory (Ocm) Physical Bank Parallelism
Method and Apparatus for Managing Transport Operations to a Cluster Within a Processor
Method and Apparatus for Managing Transfer of Transport Operations from a Cluster in a Processor
Method and Apparatus for Assigning Resources Used to Manage Transport Operations Between Clusters Within a Processor
Method and Apparatus for Managing Processing Thread Migration Between Clusters Within a Processor
Lookup Front End Packet Output Processor
Incremental Update
Packet Classification
Lookup Front End Packet Input Processor
Identifying Duplication in Decision Trees
Decision Tree Level Merging
Method and Apparatus for Power Control
Incremental Update Heuristics
Rule Modification in Decision Trees
Batch Incremental Update
Duplication in Decision Trees
Scope in Decision Trees
Patent:
9,195,939 →
Application:
13/840,867 →
Multi-Host Processing
Patent:
9,531,647 →
Application:
13/841,743 →
Packet Extraction Optimization in a Network Processor
Phased Bucket Pre-Fetch in a Network Processor
Method and Apparatus for Data Packet Integrity Checking in a Processor
Method and Apparatus for Scheduling Rule Matching in a Processor
Method and an Accumulator Scoreboard for Out-of-Order Rule Response Handling
System And Method Of Compression And Decompression
Compiler with Mask Nodes
Patent:
9,595,003 →
Application:
13/896,798 →
Lookup Cluster Complex
Deterministic Finite Automata Graph Traversal With Nodal Bit Mapping
Input Output Bridging
Level-Up Shifter Circuit for High Speed and Low Power Applications
Method and Apparatus for Compilation of Finite Automata
Clock Gated Delay Line Based On Setting Value
Clock Distribution Circuit with Distributed Delay Locked Loop
Method and Apparatus for Processing Finite Automata
System And Method To Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports
Messaging with Flexible Transmit Ordering
Memory Interface With Integrated Tester
Merged TLB Structure For Multiple Sequential Address Translations
Collapsed Address Translation With Multiple Page Sizes
Maintenance Of Cache And Tags In A Translation Lookaside Buffer
Translation Bypass In Multi-Stage Address Translation
Method and Apparatus for Managing Global Chip Power on a Multicore System on Chip
Auto-Blow Memory Repair
Content Search Mechanism That Uses A Deterministic Finite Automata (DFA) Graph, A DFA State Machine, And A Walker Process
Dynamically Adjusting Supply Voltage Based On Monitored Chip Temperature
Method and Apparatus for Reference Voltage Calibration in a Single-Ended Receiver
Method and Apparatus for Amplifier Offset Calibration
Method and Apparatus for Calibrating an Input Interface
Clock Multiplexing and Repeater Network
Method And Apparatus For Supporting Wide Operations Using Atomic Sequences
Data Strobe Generation
Method And Apparatus For Conditional Storing Of Data Using A Compare-And-Swap Based Approach
Method and Apparatus for Aligning Signals
Method and Apparatus to Represent a Processor Context with Fewer Bits
Lookup Front End Packet Output Processor
Lookup Front End Packet Input Processor
Method and Apparatus for Processing of Finite Automata
Method and Apparatus for Managing Write Back Cache
Method And Apparatus For Optimizing Finite Automata Processing
Finite Automata Processing Based on a Top of Stack (TOS) Memory
Multiple Ethernet Ports and Port Types Using a Shared Data Path
System and Method to Traverse a Non-Deterministic Finite Automata (NFA) Graph Generated for Regular Expression Patterns with Advanced Features
Generating a Non-Deterministic Finite Automata (NFA) Graph for Regular Expression Patterns with Advanced Features
Method and Apparatus for Memory Access Management
Cdr Voter with Improved Frequency Offset Tolerance
Partitioned Error Code Computation
Packet Output Processing
Method And Apparatus For Power Gating Hardware Components In A Chip Device
Packet Scheduling in a Network Processor
Packet Shaping in a Network Processor
System on Chip Link Layer Protocol
Scannable Flop with a Single Storage Element
Inter-Chip Interconnect Protocol for a Multi-Chip System
Method and System for Work Scheduling in a Multi-Chip System
Method and System for Ordering I/O Access in a Multi-Node Environment
Method and Apparatus for Memory Allocation in a Multi-Node System
Merging Independent Writes, Separating Dependent And Independent Writes, And Error Roll Back
NSP Manager
Multiplexer Flop
Work Migration in a Processor
Compilation of Finite Automata Based on Memory Hierarchy
Processing Of Finite Automata Based On Memory Hierarchy
Memory Management for Finite Automata Processing
Processing of Finite Automata Based on a Node Cache
Engine Architecture for Processing Finite Automata
Content Search Mechanism That Uses A Deterministic Finite Automata (DFA) Graph, A DFA State Machine, And A Walker Process
Secure Software and Hardware Association Technique
Method and Apparatus for a Virtual System on Chip
Method and Apparatus for a Virtual System on Chip
System and Method to Provide Non-Coherent Access to a Coherent Memory System
Method And Apparatus For Power Control
Word Boundary Lock
Traversal With Arc Configuration Information
Adder Decoder
Programmable Validation of Transaction Requests
Programmable Ordering and Prefetch
Register Access Control Among Multiple Devices
Arbitrated Access To Resources Among Multiple Devices
Independent Ordering Of Independent Transactions
Application:
14/540,656 →
Publication:
US 2016/0139806
Bypass Fifo for Multiple Virtual Channels
Packet Classification
Phased Bucket Pre-Fetch in a Network Processor
Method And Apparatus For Managing Processing Thread Migration Between Clusters Within A Processor
Dram Address Protection
Anchored Patterns
Multi-Function Delay Locked Loop
Lookup Cluster Complex
Work Request Processor
Messaging with Flexible Transmit Ordering
Qos Based Dynamic Execution Engine Selection
Reverse Nfa Generation and Processing
Scope In Decision Trees
Automatic Data Rate Matching
Voltage-Controlled Oscillator with Improved Tuning Curve Linearization
Patent:
9,673,753 →
Application:
15/000,840 →
Content Search Pattern Matching Using Deterministic Finite Automata (Dfa) Graphs
Method and Apparatus for Dynamic Virtual System on Chip
Edge Rate Control Calibration
Patent:
9,590,797 →
Application:
15/143,282 →
Voltage Regulator with Adaptive Bias Network
System and Method for Rule Matching in a Processor
Method and Apparatus for Virtualization
Method for Work Scheduling in a Multi-Chip System
Phase Measurement and Correction Circuitry
Patent:
9,698,808 →
Application:
15/335,816 →
Process-Compensated Level-Up Shifter Circuit
Collapsed Address Translation with Multiple Page Sizes
Duty Cycle Correction Method
Signal Presence Detection Circuit And Method
Method and Apparatus for Virtualization
Method and Apparatus for Managing Global Chip Power on a Multicore System on Chip
Frequency Divider
Multiple Ethernet Ports and Port Types Using a Shared Data Path
Multi-Phase Divider
Patent:
9,966,964 →
Application:
15/602,774 →
Engine Architecture for Processing Finite Automata
Baseline Wander Compensation
Method And Circuit For Low Voltage Current-Mode Bandgap
Patent:
10,222,817 →
Application:
15/721,236 →
Serializer/Deserializer (SerDes) Lanes with Lane-by-Lane Datarate Independence
Multi-Termination Scheme Interface
Self-Biased Current Trimmer With Digital Scaling Input
Modular Serializer and Deserializer
Patent:
10,141,949 →
Application:
15/805,631 →
Method And Apparatus For Multi-Band Voltage-Controlled Oscillator (VCO) Band Selection
Combined Conditional Branch and Indirect Branch Target Predictor
Limiting Backpressure With Bad Actors
Method To Limit Packet Fetching With Uncertain Packet Sizes To Control Line Rate
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 17, 2016
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: CAVIUM, INC.
Reel/Frame 038622/0066 →
Security Agreement
Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
Release of Security Interest
Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
Assignment of Assignor's Interest
Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
Assignment of Assignor's Interest
May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →