Scannable flop with a single storage element
View Patent ↗In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element and at least two legs, including a data leg and at least one scan leg. The first node of the storage element may be driven by the data leg. The opposite node of the storage element may be driven by at least one of the scan legs. The slave latch may be coupled to the master latch.
1. A flip flop circuit comprising:
a master latch comprising a storage element, at least two legs including a data leg and at least one scan leg, a first node of the storage element being driven by the data leg, an opposite node of the storage element being driven by the at least one scan leg; and
a slave latch coupled to the master latch,
wherein the flip flop circuit has a single clock input and each leg receives the single clock input, and the at least one scan leg comprises a plurality of scan legs and the data leg performs a logical OR on a plurality of scan mode inputs.
2. The flip flop circuit of claim 1 , wherein a slave data input of the slave latch is connected to the first node of the storage element.
3. The flip flop circuit of claim 1 , wherein each leg has a data input that drives an inverter buffer, an output of the inverter buffer driving a transmission gate, an output of the transmission gate driving the storage element.
4. The flip flop circuit of claim 1 , wherein the storage element comprises inverter buffers, where at least two of the inverter buffers oppose each other, and each inverter buffer is enabled by a respective generated clock received from each respective leg, and each inverter buffer receives data driven from each leg.
5. The flip flop circuit of claim 1 , wherein the slave latch comprises a transmission gate that drives a slave storage element.
6. The flip flop circuit of claim 1 , wherein the slave latch has a data input that drives an inverter buffer, an output of the inverter buffer driving a transmission gate, an output of the transmission gate driving a slave storage element, the slave storage element driving an output inverter buffer.
7. The flip flop circuit of claim 1 , wherein each given leg of the at least two legs comprises a corresponding combinatorial logic block with a scan mode input and the single clock input, the output of the corresponding combinatorial logic block generating a clock, the generated clock enabling a given data output of the respective leg.
8. The flip flop circuit of claim 7 , wherein the corresponding combinatorial logic block is a two-input NOR gate.
9. The flip flop circuit of claim 7 , wherein the generated clock is inverted for an active low enable input, to enable the given data output of the respective leg.