Patent Assignment
Reel/Frame 046496/0001
Release of Security Interest
Recorded: 2018-07-06
Pages: 65
Assignor
JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Executed: 2018-07-06
Assignees
CAVIUM, INC
2315 N. FIRST STREET, SAN JOSE, CALIFORNIA, 95131
CAVIUM NETWORKS LLC
2315 N. FIRST STREET, SAN JOSE, CALIFORNIA, 95131
QLOGIC CORPORATION
2315 N. FIRST STREET, SAN JOSE, CALIFORNIA, 95131
Covered Properties
(765)
Synchronization Circuit for Transferring Pointer Between Two Asynchronous Circuits
Patent:
6,055,285 →
Application:
08/971,387 →
State Dependent Synchronization Circuit Which Synchronizes Leading and Trailing Edges of Asynchronous Input Pulses
Patent:
6,163,550 →
Application:
08/972,117 →
Ofdm Receiving System
Patent:
6,151,295 →
Application:
09/030,865 →
Interface Module with Protection Circuit and Method of Protecting an Interface
Patent:
6,167,321 →
Application:
09/104,731 →
Method and Circuit for Receiving Dual Edge Clocked Data
Patent:
6,317,842 →
Application:
09/249,873 →
Bus Driver with Data Dependent Drive Strength Control Logic
Patent:
6,229,845 →
Application:
09/257,803 →
Systems and Methods for Network and I/O Device Drivers
Patent:
6,470,397 →
Application:
09/280,506 →
Add-On Card with Automatic Bus Power Line Selection Circuit
Patent:
6,327,635 →
Application:
09/281,369 →
Host Adapter for Combining I/O Completion Reports and Method of Using the Same
Patent:
6,434,630 →
Application:
09/282,341 →
Method and Apparatus for Automatically Transferring I/O Blocks Between a Host System and a Host Adapter
High Performance Switch Fabric Element and Switch Systems
Patent:
6,697,359 →
Application:
09/346,793 →
High Performance Switching
Patent:
6,597,691 →
Application:
09/386,109 →
Secure Virtual Interface
Secure Multiprotocol Interface
Random Number Generator
Patent:
6,954,770 →
Application:
09/938,166 →
Method and Apparatus for Performing Computations and Operations on Data Using Data Steering
Method and Apparatus for Establishing Secure Sessions
Interface for a Security Coprocessor
Patent:
6,789,147 →
Application:
10/025,512 →
Method and Apparatus to Implement the Data Encryption Standard Algorithm
Patent:
7,076,059 →
Application:
10/052,054 →
Method and Apparatus for Montgomery Multiplication
Patent:
7,035,889 →
Application:
10/068,677 →
On-Chip Inter-Subsystem Communication
Speculative Execution for Data Ciphering Operations
Patent:
7,260,217 →
Application:
10/092,328 →
Router and Methods Using Network Addresses for Virtualization
Fibre Channel Credit Extender and Repeater
System and Method for Eventless Detection of Newly Delivered Variable Length Messages from a System Area Network
Method and System for Dynamically Assigning Domain Identification in a Multi-Module Fibre Channel Switch
Method and System for Primary Blade Selection in a Multi-Module Fibre Channel Switch
System and Method for Optimizing Frame Routing in a Network
Patent:
7,334,046 →
Application:
10/212,425 →
Dual-Mode Network Storage Systems and Methods
Decoupled Architecture for Data Ciphering Operations
Patent:
7,305,567 →
Application:
10/234,895 →
Zone Management in a Multi-Module Fibre Channel Switch
Patent:
7,397,768 →
Application:
10/241,153 →
Method and System for Using Distributed Name Servers in Multi-Module Fibre Channel Switches
Patent:
7,362,717 →
Application:
10/263,858 →
Router with Routing Processors and Methods for Virtualization
Router and Methods for Distributed Virtualization
Method and System for Reworking Ball Grid Arrays
Patent:
6,769,596 →
Application:
10/295,976 →
Hardware-Enforced Loop-Level Hard Zoning for Fibre Channel Switch Fabric
Method and Apparatus for Automatically Transferring I/O Blocks Between a Host System and a Host Adapter
Apparatus and Method for Repairing Logic Blocks
Patent:
6,861,865 →
Application:
10/387,151 →
Apparatus and Method for Data Deskew
Patent:
7,209,531 →
Application:
10/397,083 →
Method and System for Calibrating Scsi Expanders
Patent:
6,959,345 →
Application:
10/410,773 →
Transparent Ipsec Processing Inline Between a Framer and a Network Component
Apparatus and Method for Allocating Resources Within a Security Processing Architecture Using Multiple Groups
Apparatus and Method for Allocating Resources Within a Security Processing Architecture Using Multiple Queuing Mechanisms
Apparatus and Method for Allocating Resources Within a Security Processor
Ipsec Performance Optimization
Method and System for Processing Non-Data Frames in Host Bus Adapters
Patent:
6,961,784 →
Application:
10/417,523 →
On-Chip Packet-Based Interconnections Using Repeaters/Routers
Patent:
6,996,785 →
Application:
10/423,499 →
Method and System for Providing a Virtual Universal Serial Port Interface and a Virtual Storage Interface
Patent:
7,424,419 →
Application:
10/445,695 →
Security System with an Intelligent Dma Controller
Subsystem Boot and Peripheral Data Transfer Architecture for a Subsystem of a System-on- Chip
System and Method for Improving Dynamic Range of Analog-to Digital Converters
Patent:
6,864,814 →
Application:
10/600,779 →
Synchronizing Method and Apparatus
Method and System for Processing Network Data Packets
Patent:
7,515,612 →
Application:
10/619,719 →
Method and System for Processing Network Data Packets
Patent:
7,403,542 →
Application:
10/620,040 →
Buffer to Buffer Credit Recovery for in-Line Fibre Channel Credit Extension Devices
Patent:
7,352,701 →
Application:
10/664,548 →
Method and System for Providing Data Integrity in Storage Systems
Patent:
7,234,101 →
Application:
10/674,943 →
System and method for testing ball grid arrays
Patent:
7,009,413 →
Application:
10/683,622 →
Method and System for Minimizing Memory Corruption
Patent:
7,219,263 →
Application:
10/696,471 →
Method and System for Monitoring Events in Storage Area Networks
Patent:
7,103,504 →
Application:
10/719,077 →
Mosfet-Fused Nonvolatile Read-Only Memory Cell (Mofrom)
Patent:
6,949,423 →
Application:
10/723,004 →
High Performance Switch Fabric Element and Switch Systems
Revision Control System for Large-Scale Systems Management
Patent:
7,231,410 →
Application:
10/797,977 →
Method and System for Reducing Deadlock in Fibre Channel Fabrics Using Virtual Lanes
Method and System for Preventing Deadlock in Fibre Channel Fabrics Using Frame Priorities
Pci - Express Slot for Coupling Plural Devices to a Host System
Method and System for Efficiently Recording Processor Events in Host Bus Adapters
Direct Hardware Processing of Internal Data Structure Fields
Patent:
7,493,481 →
Application:
10/848,485 →
Method and System for Host Device Event Synchronization
Method and Apparatus for Test Pattern Generation
Method and Apparatus for Accelerating Receive-Modify-Send Frames in a Fibre Channel Network
Method and Apparatus for Detecting and Removing Orphaned Primitives in a Fibre Channel Network
Method and System for Fibre Channel Arbitrated Loop Acceleration
Method and System for Minimizing Disruption in Common-Access Networks
Method and Apparatus for Testing Loop Pathway Integrity in a Fibre Channel Arbitrated Loop
Method and Apparatus for Improving Buffer Utilization in Communication Networks
Method and System for Non-Disruptive Data Capture in Networks
Method and System for Keeping a Fibre Channel Arbitrated Loop Open During Frame Gaps
Lun Based Hard Zoning in Fibre Channel Switches
Integrated Fibre Channel Fabric Controller
Method and System for Congestion Control Based on Optimum Bandwidth Allocation in a Fibre Channel Switch
Method and System for Routing and Filtering Network Data Packets in Fibre Channel Systems
Method and System for Using Extended Fabric Features with Fibre Channel Switch Elements
Method and System for Managing Traffic in Fibre Channel Systems
Method and System for Distributing Credit in Fibre Channel Systems
Multi-Speed Cut Through Operation in Fibre Channel Switches
Method and System for Reducing Latency and Congestion in Fibre Channel Switches
Programmable Pseudo Virtual Lanes for Fibre Channel Systems
Method and System for Programmable Data Dependant Network Routing
Method and System for Routing Fibre Channel Frames
Method and System for Power Control of Fibre Channel Switches
Method and System for Improving Bandwidth and Reducing Idles in Fibre Channel Switches
Method and System for Congestion Control in a Fibre Channel Switch
Method and System for Selecting Virtual Lanes in Fibre Channel Switches
Method and System for Configuring Fibre Channel Ports
Method and System for Programmable Data Dependant Network Routing
Method and System for Detecting Congestion and Over Subscription in a Fibre Channel Network
Self-Triggering Outgoing Buffers
Patent:
7,308,535 →
Application:
10/927,170 →
Method and System for Processing Markers, Data Integrity Fields and Digests
Method and System for Efficiently Using Buffer Space
Method and System for Optimizing Dma Channel Selection
Ensuring Buffer Availability
Patent:
7,895,390 →
Application:
10/940,355 →
High Speed Fibre Channel Switch Element
Method and System for Lun Remapping in Fibre Channel Networks
Method and System for Transferring Data Directly Between Storage Devices in a Storage Area Network
Methd and System for Using an in-Line Credit Extender with a Host Bus Adapter
Method and System for Processing Out of Order Frames
Method and System for Using Boot Servers in Networks
Fibre Channel Transparent Switch for Mixed Switch Fabrics
Method and Apparatus for Efficient Determination of Status from Dma Lists
Patent:
7,512,721 →
Application:
10/963,287 →
Method and System for Dma Optimization in Host Bus Adapters
Store Instruction Ordering for Multi-Core Processor
Packet Queuing, Scheduling and Ordering
Local Scratchpad and Data Caching System
Method and System for High Speed Network Application
Direct Access to Low-Latency Memory
Address Translation in Fibre Channel Switches
Method and System for Testing Host Bus Adapters
Apparatus and Method for Repairing Logic Blocks
Patent:
7,205,785 →
Application:
11/040,266 →
Secure Virtual Interface
Tcp Time Stamp Processing in Hardware Based Tcp Offload
System and Method of Providing Network Node Services
Elastic Buffer Module for Pci Express Devices
Method and System for Receiver Detection in Pci-Express Devices
Method and System for Asic Simulation
Method and System for High Speed Network Application
Gasket Retainer
Method and System for Testing Network Device Logic
Tcp Engine
Deterministic Finite Automata (Dfa) Instruction
Deterministic Finite Automata (Dfa) Processing
Method and System for Synchronizing Bit Streams for Pci Express Devices
Patent:
7,230,549 →
Application:
11/222,592 →
Method and System for Dma Optimization
Patent:
7,577,773 →
Application:
11/222,936 →
Dedicated Application Interface for Network Systems
Patent:
7,639,715 →
Application:
11/223,693 →
Content Search Mechanism That Uses a Deterministic Finite Automata (Dfa) Graph, a Dfa State Machine, and a Walker Process
Method and Apparatus for Reducing Host Overhead in a Socket Server Implementation
Method and System for Designing a Flexible Hardware State Machine
Patent:
7,447,874 →
Application:
11/252,524 →
Method and System for Filtering Unknown Values in Asic Design Simulation
Patent:
7,630,876 →
Application:
11/257,693 →
On-Chip Packet-Based Interconnections Using Repeaters/Routers
Patent:
7,543,250 →
Application:
11/283,210 →
Method and System for Managing Transmit Descriptors in a Networking System
Patent:
7,920,473 →
Application:
11/291,430 →
Method and System for Processing Network Data
Patent:
7,735,099 →
Application:
11/317,315 →
Method and system for port licensing in switches
Patent:
8,682,799 →
Application:
11/318,116 →
Method and System for Processing Dma Requests
Patent:
7,594,057 →
Application:
11/328,358 →
Selective Replication of Data Structures
Method and System for Managing Storage Area Networks
Patent:
8,464,238 →
Application:
11/343,596 →
Method and System for Managing Storage Area Networks
Patent:
7,496,745 →
Application:
11/346,106 →
Method and System for Sharing Input/Output Devices
Patent:
7,694,047 →
Application:
11/355,622 →
Method and System for Storing Frames in Networks
Patent:
7,668,978 →
Application:
11/357,515 →
Method and System for Managing Frame Flow in Fibre Channel Systems
Patent:
7,518,995 →
Application:
11/362,690 →
Method and System for Checking Frame-Length in Fibre Channel Frames
Patent:
7,548,560 →
Application:
11/363,365 →
Method and System for Motion Estimation with Multiple Vector Candidates
Method and System for Auto Routing Fibre Channel Class F Frames in a Fibre Channel Fabric
Patent:
7,525,968 →
Application:
11/376,955 →
Method and System for Dynamically Adjusting Data Transfer Rates in Pci-Express Devices
Patent:
7,461,195 →
Application:
11/378,838 →
Byte Level Protection in Pci-Express Devices
On-Chip Inter-Subsystem Communication
Method and System for Processing Arbitration Requests
Patent:
7,447,817 →
Application:
11/430,704 →
Method and System for Inter-Fabric Routing
Method and System for Processing Network Information
Patent:
7,764,676 →
Application:
11/461,387 →
Method and System for Using Application Specific Integrated Circuits
Patent:
7,669,001 →
Application:
11/469,377 →
Method and System for Managing Boot Trace Information in Host Bus Adapters
Patent:
7,610,482 →
Application:
11/477,161 →
Method and System for Testing Integrated Circuits
Patent:
7,379,837 →
Application:
11/491,357 →
System and Method for Managing Access to Adapter Features
Patent:
8,185,960 →
Application:
11/493,978 →
Method and System for Processing Asynchronous Event Notifications
Patent:
7,457,887 →
Application:
11/502,282 →
Method and System for Processing Network Information
Patent:
7,843,846 →
Application:
11/522,672 →
Method and System for Routing Network Information
Patent:
7,773,592 →
Application:
11/533,873 →
Method and System for Processing Network Information
Patent:
8,004,991 →
Application:
11/548,421 →
Method and System for Data Transfer
Patent:
8,601,179 →
Application:
11/555,123 →
Method and System for Writing Network Data
Patent:
8,055,726 →
Application:
11/555,180 →
Method and System for Routing Network Information
Patent:
7,613,816 →
Application:
11/560,317 →
Method and System for Real Time Compression and Decompression
Patent:
7,643,505 →
Application:
11/565,444 →
Method and System for Primary Blade Selection in a Multi-Module Fibre Channel Switch
System and Method for Managing Interrupts
Patent:
7,549,005 →
Application:
11/615,329 →
Switching Systems and Methods Using Wildcard Searching
Patent:
7,774,374 →
Application:
11/617,716 →
Method and System for Quality of Service in Host Bus Adapters
Patent:
7,668,177 →
Application:
11/669,573 →
Compression and Decompression for Network Systems
Patent:
7,668,162 →
Application:
11/669,775 →
Zone Management in a Multi-Module Fibre Channel Switch
Patent:
7,729,288 →
Application:
11/682,199 →
Congestion Reducing Reliable Transport Packet Retry Engine
Method and System for Managing Metadata in Storage Virtualization Environment
Patent:
8,185,715 →
Application:
11/694,698 →
Method and System for Processing Network Packets
Patent:
8,387,073 →
Application:
11/742,282 →
Revision Control System for Large-Scale Systems Management
Method and System for Network Traffic Monitoring
Patent:
8,250,203 →
Application:
11/752,212 →
Method and System for Managing Ports in a Host Bus Adapter
Patent:
8,095,978 →
Application:
11/761,279 →
Method and System for Network Communication
Patent:
8,102,769 →
Application:
11/762,578 →
Hardware-Enforced Loop-Level Hard Zoning for Fibre Channel Switch Fabric
Method and System for Processing Layered Networking Protocol Packets
Patent:
8,411,677 →
Application:
11/842,830 →
Dual-Mode Network Storage Systems and Methods
Patent:
7,688,867 →
Application:
11/845,688 →
Resistively Loaded Single Stage Differential Amplifier Having Zero Volt Common Mode Input
Hardware-Enforced Loop and Npiv Hard Zoning for Fibre Channel Switch Fabric
Method and System for Monitoring a Network Link in Network Systems
Patent:
7,903,558 →
Application:
11/864,651 →
Self-Trigerring Outgoing Buffers
Direct Hardware Processing of Internal Data Structure Fields
Patent:
8,555,260 →
Application:
11/949,755 →
Method and System for Processing Network and Storage Data
Patent:
7,720,064 →
Application:
11/963,566 →
Method and System for Securing Network Data
Patent:
8,010,809 →
Application:
11/965,037 →
System and Method for Assigning Network Device Port Address Based on Link Rate
Patent:
7,719,969 →
Application:
11/966,857 →
Graph Caching
Intelligent Graph Walking
Deterministic Finite Automata (Dfa) Graph Compression
Method and Apparatus for Traversing a Compressed Deterministic Finite Automata (Dfa) Graph
Method and System for Credit Management in a Networking System
Patent:
7,609,710 →
Application:
12/019,094 →
Fibre Channel Transparent Switch for Mixed Switch Fabrics
Method and System for Communicating with a Host Bus Adapter
Patent:
7,962,675 →
Application:
12/034,913 →
Method and System for Routing Frames in a Network
Patent:
8,116,206 →
Application:
12/037,847 →
Systems and Methods for Testing Device Ports in a Storage Area Network
Patent:
7,895,300 →
Application:
12/039,604 →
Method and System for Managing Network and Storage Data
Patent:
7,908,404 →
Application:
12/052,130 →
Method and System for Selection of Reference Picture and Mode Decision
Power Management for Host Bus Adapters
Patent:
8,904,077 →
Application:
12/111,057 →
Method and System for Network Port Addressing
Patent:
7,773,629 →
Application:
12/135,973 →
Programmable Pseudo Virtual Lanes for Fibre Channel Systems
System and Methods for Locating Fpdu Headers When Markers Are Disabled
Patent:
7,765,317 →
Application:
12/165,464 →
Memory Management in a Network Adapter
Patent:
8,619,558 →
Application:
12/176,750 →
Method and System for Managing Traffic in Fibre Channel Systems
Method and System for Routing Fibre Channel Frames
Method and System for Keeping a Fibre Channel Arbitrated Loop Open During Frame Gaps
Method and Apparatus for Detecting and Removing Orphaned Primitives in a Fibre Channel Network
Computer Network Device and Method of Assembly
Patent:
7,667,985 →
Application:
12/200,649 →
Apparatus and Methods for Cooling Network Switches
Patent:
7,646,602 →
Application:
12/201,304 →
Apparatus and Methods for Cooling Network Switches
Patent:
7,675,750 →
Application:
12/201,359 →
Single-Ended to Differential Converter
Method and Apparatus for Content Based Searching
Fibre Channel Credit Extender and Repeater
Method and System for Power Control of Fibre Channel Switches
Deterministic Finite Automata Graph Traversal with Nodal Bit Mapping
Multiple core Session Initiation Protocol (SIP)
Method and System for Processing Network Data Packets
Patent:
7,830,919 →
Application:
12/389,308 →
Secure Software and Hardware Association Technique
Method and System for Efficiently Using Buffer Space
Network Device with Baffle for Redirecting Cooling Air and Associated Methods
Patent:
8,068,338 →
Application:
12/410,277 →
Network Device Having Levers and Associated Methods
Patent:
7,907,414 →
Application:
12/410,294 →
Method and System for Port Negotiation
Patent:
7,907,546 →
Application:
12/411,176 →
Method and System for Taking a Network Port Offline
Patent:
9,094,343 →
Application:
12/412,050 →
Method and System for Multi-Level Switch Configuration
Patent:
8,060,682 →
Application:
12/415,873 →
Method and System for Transmitting Flow Control Information
Patent:
8,089,971 →
Application:
12/423,626 →
Method and System for Selecting Virtual Lanes in Fibre Channel Switches
Flexible Server Network Connection Upgrade Systems and Methods
Patent:
8,069,293 →
Application:
12/471,331 →
Method and System for Configuring Fibre Channel Ports
Method and System for Processing Network Packets
Patent:
8,296,386 →
Application:
12/489,241 →
Multi-Speed Cut Through Operation in Fibre Channel Switches
Profile-Based and Dictionary Based Graph Caching
Application:
12/505,324 →
Publication:
US 2011/0016154
Method and System for Network Communication
Patent:
8,351,442 →
Application:
12/505,430 →
Method and System for Accelerating Network Packet Processing
Patent:
8,793,399 →
Application:
12/536,336 →
Configurable Switch Element and Methods Thereof
Patent:
8,391,300 →
Application:
12/539,156 →
System and Method for Mapping Functions to and from Network Devices Using Configuration Compatible with an Adapter by Remapping Plurality of Logical Ports of Adapter
Patent:
8,065,454 →
Application:
12/544,658 →
Emulation of Multiple Mdio Manageable Devices
Patent:
8,200,473 →
Application:
12/547,414 →
System and Methods for Inter-Driver Communication
Patent:
8,978,052 →
Application:
12/551,302 →
Method and System for Controlling Power Consumption in Network Nodes
Patent:
8,155,022 →
Application:
12/552,222 →
Method and System for Network Switch Element
System and Methods for Managing Virtual Adapter Instances
Patent:
8,671,228 →
Application:
12/572,810 →
System and Method to Process Event Reporting in an Adapter
Patent:
8,504,750 →
Application:
12/572,835 →
Method and Apparatus for Reducing Host Overhead in a Socket Server Implementation
Method and System for Buffer-to-Buffer Credit Recovery in Fibre Channel Systems Using Virtual and/or Pseudo Virtual Lanes
Dll-Based Temperature Sensor
Method and Apparatus for Correcting Linear Error Phase of an Ofdm Signal
Method and System for Tag Arbitration in Switches
Patent:
8,116,311 →
Application:
12/615,152 →
Concurrent Transmit Processing
Patent:
7,970,927 →
Application:
12/651,270 →
Compression and Decompression for Network Systems
Patent:
7,889,730 →
Application:
12/684,054 →
System and Methods for Data Migration
Patent:
9,329,794 →
Application:
12/691,629 →
Method and Apparatus for Estimating Overshoot Power After Estimating Power of Executing Events
Method and System for Using Extended Fabric Features with Fibre Channel Switch Elements
Patent:
7,990,975 →
Application:
12/697,994 →
System and Methods for Presenting Storage
Patent:
8,406,152 →
Application:
12/730,139 →
Method and System for Extended Port Addressing
Patent:
8,351,448 →
Application:
12/731,065 →
Method and System for Processing Network and Storage Data
Patent:
8,225,004 →
Application:
12/751,955 →
Systems and Methods for Bandwidth Scavenging Among a Plurality of Applications in a Network
Patent:
8,307,111 →
Application:
12/759,316 →
Method and Apparatus for a Virtual System on Chip
Method and System for Load Balancing in Networks
Patent:
8,705,351 →
Application:
12/774,574 →
System and Method for Low-Latency Multimedia Streaming
Method and System for Communication with an Adapter
Patent:
8,315,268 →
Application:
12/795,563 →
System and Method to Restore Maximum Payload Size in a Network Adapter
Patent:
8,185,664 →
Application:
12/817,707 →
System and Methods for Using a Dma Module for a Plurality of Virtual Machines
Patent:
8,250,252 →
Application:
12/826,105 →
System and Method for Enabling Access to a Protected Hardware Resource
Method and System for Routing Information in a Network
Patent:
8,706,905 →
Application:
12/859,690 →
System and Methods for Migrating Information from Source Storage to Destination Storage
Patent:
8,510,527 →
Application:
12/901,409 →
Systems and Methods for Efficiently Processing Large Data Segments
Patent:
8,386,644 →
Application:
12/901,994 →
Ring Bus for Sharing Resources Among Multiple Engines
Patent:
8,301,817 →
Application:
12/902,020 →
Method and System for Communication Across Multiple Channels
Patent:
8,478,909 →
Application:
12/914,852 →
Selectable Initialization for Adapters
Patent:
8,566,573 →
Application:
12/941,621 →
Facilitating Communication Between Devices in a Network
Patent:
9,426,097 →
Application:
12/964,295 →
System and Method for Optimizing Use of Channel State Information
Method and System for Monitoring a Network Link in Network Systems
Patent:
8,441,929 →
Application:
13/026,007 →
Simulation System and Method Thereof
Patent:
8,682,632 →
Application:
13/029,018 →
Method and System for Application Isolation
Patent:
8,880,732 →
Application:
13/035,114 →
On-Demand Intra-Refresh for End-to End Coded Video Transmission Systems
Low latency rate control system and method
Video encoder bit estimator for macroblock encoding
System and Method of Compression and Decompression
System and Method for Secure Device Key Storage
Compression with Adjustable Quality/Bandwidth Capability
Concurrent Transmit Processing
Patent:
8,275,903 →
Application:
13/111,475 →
Anchored Patterns
Regular Expression Processing Automaton
Regex Compiler
Method and System for Using Extended Fabric Features with Fibre Channel Switch Elements
Patent:
8,644,317 →
Application:
13/177,314 →
Method and System for Link Aggregation
Patent:
8,467,395 →
Application:
13/181,251 →
Method and System for Link Aggregation
Patent:
8,488,601 →
Application:
13/181,270 →
Secure Software and Hardware Association Technique
Method and System for Securing Network Data
Patent:
8,261,099 →
Application:
13/190,165 →
Method and System for Managing Network Elements
Method and System for Congestion Management in Networks
Patent:
8,441,922 →
Application:
13/216,598 →
Methods and Systems for Processing Network Information
Patent:
8,798,047 →
Application:
13/220,249 →
System and Method for Mapping Functions to and from Network Devices Using Configuration Compatible with an Adapter by Remapping Plurality of Logical Ports of Adapter
Patent:
8,225,018 →
Application:
13/221,737 →
Method and System for Memory Management
Method and System for Writing Network Data
Patent:
8,676,928 →
Application:
13/241,012 →
Processor with Dedicated Virtual Functions and Dynamic Assignment of Functional Resources
Qos Based Dynamic Execution Engine Selection
Method and System for Network Switch Element
Processor With Efficient Work Queuing
Packet Priority in a Network Processor
System and Method to Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports
System and Method to Provide Non-Coherent Access to a Coherent Memory System
Input Output Bridging
Multi-Protocol Serdes Phy Apparatus
Word Boundary Lock
Bit Error Rate Impact Reduction
Packet Traffic Control in a Network Processor
Network Processor with Distributed Trace Buffers
Multi-Core Interconnect in a Network Processor
Work Request Processor
Reverse Nfa Generation and Processing
Graph Caching
Dram Address Protection
Messaging with Flexible Transmit Ordering
Systems and Methods for Sending and Receiving Information via a Network Device
Patent:
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Application:
13/328,919 →
Method and System for Network Communication
Patent:
8,792,351 →
Application:
13/330,085 →
Differential Amplifier with Duty Cycle Compensation
State Machine for Deskew Delay Locked Loop
Level-Up Shifter Circuit
Multi-Function Delay Locked Loop
Memory Interface with Selectable Evaluation Modes
Electronic Devices Having Cooling Module with Direction-Configurable Airflow
Patent:
8,873,236 →
Application:
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Synchronized Clock Phase Interpolator
Differential Amplifier with De-Emphasis
Tools, Systems, and Methods for Removing Connectors from Ports in a Network Device
Patent:
8,893,366 →
Application:
13/403,697 →
Flexible Edge Access Switch and Associated Methods Thereof
Patent:
8,953,606 →
Application:
13/433,146 →
Method and System for Offloading Copy on Write Operations
Patent:
9,164,913 →
Application:
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System and Method to Restore Maximum Payload Size in a Network Adapter
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8,996,730 →
Application:
13/447,652 →
High Speed Variable Bandwidth Ring-Based System
System and Methods for Using a Dma Module for a Plurality of Virtual Machines
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Application:
13/489,016 →
System and Method for Storing Lookup Request Rules in Multiple Memories
Method and Apparatus Encoding a Rule for a Lookup Request in a Processor
System and Method for Rule Matching in a Processor
Lookup Cluster Complex
Work Migration in a Processor
Lookup Front End Packet Input Processor
Method and Apparatus for Multiple Access of Plural Memory Banks
On-Chip Memory (Ocm) Physical Bank Parallelism
Method and Apparatus for Managing Transport Operations to a Cluster Within a Processor
Method and Apparatus for Managing Transfer of Transport Operations from a Cluster in a Processor
Method and Apparatus for Assigning Resources Used to Manage Transport Operations Between Clusters Within a Processor
Method and Apparatus for Managing Processing Thread Migration Between Clusters Within a Processor
Lookup Front End Packet Output Processor
Incremental Update
Packet Classification
System and Method for High Speed Multiple Buffer Allocation
Patent:
9,229,791 →
Application:
13/594,343 →
Lookup Front End Packet Input Processor
High Speed Fibre Channel Switch Element
Method and System for Processing Network Packets
Patent:
8,867,537 →
Application:
13/610,095 →
Systems and Methods for Bandwidth Scavenging Among a Plurality of Applications in a Network
Patent:
9,003,038 →
Application:
13/644,203 →
Method and System for Communication Between a Computing System and a Device
Patent:
9,256,562 →
Application:
13/644,535 →
Method and System for Communication Between a Computing Device and a Peripheral Device
Patent:
9,727,494 →
Application:
13/649,391 →
Method and System for Arbitration Verification
Patent:
9,069,919 →
Application:
13/654,308 →
Method and System for Communication Using Multiple Dma Channels
Patent:
8,677,044 →
Application:
13/660,928 →
Identifying Duplication in Decision Trees
Network Device Scheduler and Methods Thereof
Patent:
8,995,425 →
Application:
13/678,047 →
Systems and Methods for Hard Zoning in Networks
Patent:
8,989,191 →
Application:
13/678,055 →
Cut-Through Routing for Network Devices
Patent:
9,444,713 →
Application:
13/678,086 →
Systems and Methods for Rate Matching in Networks Utilizing a Strobe Counter
Patent:
8,924,764 →
Application:
13/678,100 →
Memory Devices for Network Devices and Associated Methods
Patent:
8,995,455 →
Application:
13/678,108 →
Systems and Methods for Processing Information by a Network Device
Patent:
9,225,808 →
Application:
13/678,121 →
Systems and Methods for Quality of Service in Networks
Patent:
9,172,655 →
Application:
13/678,135 →
Method and System for Programmable Delay Before Transmission Pausing
Patent:
8,976,667 →
Application:
13/678,145 →
Systems and Methods for Modifying Frames in a Network Device
Patent:
8,995,457 →
Application:
13/678,161 →
Network Devices Having Configurable Receive Packet Queues and Related Methods
Patent:
9,071,559 →
Application:
13/678,367 →
Systems and Methods for Using Tcams in Network Devices
Patent:
8,996,798 →
Application:
13/678,377 →
Systems and Methods for Routing by Network Devices
Patent:
9,426,063 →
Application:
13/678,378 →
Systems and Methods for Packet Grouping in Networks
Patent:
9,225,672 →
Application:
13/678,385 →
Systems and Methods for Primitive Sequence Capture and Retransmission in a Network Device
Patent:
9,049,113 →
Application:
13/678,397 →
System and Method for Sharing Logic in a Network Device
Patent:
9,046,941 →
Application:
13/678,398 →
Method and System for Using Lane Alignment Markers
Patent:
9,172,661 →
Application:
13/678,406 →
Methods and Systems for an Out-of-Credit Timer in a Network Device
Patent:
9,094,294 →
Application:
13/678,411 →
Method and System for Auto-Negotiation
Patent:
9,172,602 →
Application:
13/678,418 →
Decision Tree Level Merging
Methods and Systems for Processing Commands by a Device Interfacing with a Computing System
Patent:
9,047,151 →
Application:
13/689,607 →
Method and System for Extended Port Addressing
Patent:
9,071,558 →
Application:
13/711,380 →
Method and Apparatus for Power Control
Method and System for Using Asymetric Transfer Rates in Receive and Transmit Paths of a Network
Patent:
8,948,203 →
Application:
13/755,770 →
Configurable Switch Element and Methods Thereof
Patent:
8,976,800 →
Application:
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Systems and Methods for Identifying Port Protocols Using Leds
Patent:
9,384,113 →
Application:
13/762,715 →
System and Methods for Presenting Storage
Patent:
8,873,430 →
Application:
13/770,828 →
Method and System for Inserting Cookies in I/O Commands
Patent:
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Application:
13/782,673 →
Intelligent Adapter for Providing Storage Area Network Access and Access to a Local Storage Device
Intelligent Adapter for Maintaining Cache Coherency
Patent:
9,330,003 →
Application:
13/790,471 →
In-Band Management Using an Intelligent Adapter and Methods Thereof
Patent:
9,507,524 →
Application:
13/790,499 →
Methods and Systems for an Intelligent Storage Adapter Used for Both San and Local Storage Access
Patent:
9,232,005 →
Application:
13/790,846 →
Apparatus and Method for Media Access Control Scheduling with a Sort Hardware Coprocessor
Apparatus and Method for Media Access Control Scheduling with a Priority Calculation Hardware Coprocessor
Smoothing Fifo and Methods Thereof
Patent:
9,282,046 →
Application:
13/830,717 →
Incremental Update Heuristics
Rule Modification in Decision Trees
Batch Incremental Update
Duplication in Decision Trees
Method and System for Frame Aggregation
Patent:
8,953,608 →
Application:
13/834,838 →
Scope in Decision Trees
Patent:
9,195,939 →
Application:
13/840,867 →
Multi-Host Processing
Patent:
9,531,647 →
Application:
13/841,743 →
Packet Extraction Optimization in a Network Processor
Phased Bucket Pre-Fetch in a Network Processor
Method and Apparatus for Data Packet Integrity Checking in a Processor
Method and Apparatus for Scheduling Rule Matching in a Processor
Method and an Accumulator Scoreboard for Out-of-Order Rule Response Handling
Method and System for Detecting Loss of Synchronization in Ports
Patent:
9,143,415 →
Application:
13/852,872 →
Method and System for Variable Length Tag Processing
Patent:
9,100,334 →
Application:
13/852,885 →
System and Method to Process Event Reporting in an Adapter
Patent:
9,043,519 →
Application:
13/856,848 →
System And Method Of Compression And Decompression
Compiler with Mask Nodes
Patent:
9,595,003 →
Application:
13/896,798 →
Lookup Cluster Complex
Method and System for Writing Tag and Data
Patent:
9,172,586 →
Application:
13/902,427 →
Method and System for Transmitting Information from a Network Device
Patent:
9,747,227 →
Application:
13/902,453 →
Deterministic Finite Automata Graph Traversal With Nodal Bit Mapping
Input Output Bridging
Method and System for Processing Write Requests
Patent:
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Application:
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Apparatus and Method for Uniquely Enumerating Paths in a Parse Tree
Application:
13/921,090 →
Publication:
US 2014/0369363
Method and System for Configuring Network Devices
Patent:
8,898,346 →
Application:
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System and Methods for Managing Networks
Patent:
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Application:
13/924,107 →
Methods and Systems for Advertsing Available Credit at Memory of Network Device Ports Based on Temperature
Patent:
9,411,400 →
Application:
13/949,095 →
Method and System for Processing Information at Peripheral Devices
Patent:
8,977,786 →
Application:
13/954,661 →
Network Information Processing and Methods Thereof
Patent:
9,118,610 →
Application:
13/959,232 →
Level-Up Shifter Circuit for High Speed and Low Power Applications
Method and System for Determining Drop Eligibility of Network Information
Patent:
9,154,455 →
Application:
14/014,803 →
Method and Apparatus for Compilation of Finite Automata
Clock Gated Delay Line Based On Setting Value
Clock Distribution Circuit with Distributed Delay Locked Loop
Method and Apparatus for Processing Finite Automata
System And Method To Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports
Messaging with Flexible Transmit Ordering
Method and System for Data Integrity
Patent:
9,256,491 →
Application:
14/034,006 →
Systems and Methods for Routing Multicast Packets
Patent:
9,281,953 →
Application:
14/034,200 →
Memory Interface With Integrated Tester
Method and System for Memory Management
Merged TLB Structure For Multiple Sequential Address Translations
Collapsed Address Translation With Multiple Page Sizes
Maintenance Of Cache And Tags In A Translation Lookaside Buffer
Translation Bypass In Multi-Stage Address Translation
Method and Apparatus for Managing Global Chip Power on a Multicore System on Chip
Auto-Blow Memory Repair
Content Search Mechanism That Uses A Deterministic Finite Automata (DFA) Graph, A DFA State Machine, And A Walker Process
Dynamically Adjusting Supply Voltage Based On Monitored Chip Temperature
Method and Apparatus for Reference Voltage Calibration in a Single-Ended Receiver
Method and Apparatus for Amplifier Offset Calibration
Method and Apparatus for Calibrating an Input Interface
Clock Multiplexing and Repeater Network
Systems and Methods for Quality of Service for Link Aggregation Groups
Patent:
9,264,383 →
Application:
14/042,111 →
Protocol Switching over Multi-Network Interface
Method And Apparatus For Supporting Wide Operations Using Atomic Sequences
Data Strobe Generation
Method And Apparatus For Conditional Storing Of Data Using A Compare-And-Swap Based Approach
Method and Apparatus for Aligning Signals
Method and System for Data Integrity in Tcams
Patent:
9,170,880 →
Application:
14/048,849 →
Systems and Methods for High Speed Data Processing at a Network Port
Patent:
9,253,120 →
Application:
14/051,290 →
Method and System for Communication with Peripheral Devices
Patent:
9,311,268 →
Application:
14/058,887 →
Method and System for Signal Equalization in Communication Between Computing Devices
Patent:
9,424,226 →
Application:
14/062,418 →
Multiple Core Session Initiation Protocol (SIP)
Application:
14/067,524 →
Publication:
US 2014/0059241
Timers and Methods Thereof for Computing Devices
Patent:
9,465,406 →
Application:
14/067,815 →
Method and Apparatus to Represent a Processor Context with Fewer Bits
Lookup Front End Packet Output Processor
Virtualized Network Interface for Tcp Reassembly Buffer Allocation
Method and System for Remote Cache Direct Data Placement
Patent:
9,223,518 →
Application:
14/088,082 →
Method and System of Configuring Virtual Function in Peripheral Devices
Patent:
9,047,208 →
Application:
14/100,856 →
Virtualized Network Interface for Lockdown and Overlay of Data in Transmitted Packets
Virtualized Network Interface for Remote Direct Memory Access Over Converged Ethernet
Lookup Front End Packet Input Processor
System and a Method for a Remote Direct Memory Access Over Converged Ethernet
Method and an Apparatus for Memory Address Allignment
Method and an Apparatus for Virtualization of a Quality-Of-Service
Method and an Apparatus for Converting Interrupts into Scheduled Events
System for and Method of Combining Cmos Inverters of Multiple Drive Strengths to Create Tune-Able Clock Inverters of Variable Drive Strengths in Hybrid Tree-Mesh Clock Distribution Networks
System for and Method of Placing Clock Stations Using Variable Drive-Strength Clock Drivers Built Out of a Smaller Subset of Base Cells for Hybrid Tree-Mesh Clock Distribution Networks
System for and Method of Tuning Clock Networks Constructed Using Variable Drive-Strength Clock Inverters with Variable Drive-Strength Clock Drivers Built Out of a Smaller Subset of Base Cells
Apparatus and Method for Interrupt Collecting and Reporting Status and Delivery Information
Look-Aside Processor Unit with Internal and External Access for Multicore Processors
Matrix of on-Chip Routers Interconnecting a Plurality of Processing Engines and a Method of Routing Using Thereof
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Apparatus and Method for Packet Memory Datapath Processing in High Bandwidth Packet Processing Devices
Patent:
9,256,380 →
Application:
14/142,612 →
Apparatus and Method for Time Stamping Packets Across Several Nodes in a Network
Patent:
9,509,585 →
Application:
14/142,623 →
Apparatus and Method for Optimizing the Number of Accesses to Page-Reference Count Storage In Page Link List Based Switches
Patent:
9,438,539 →
Application:
14/142,631 →
Apparatus and Method for Accelerated Page Link List Processing in a Packet Processor Operating at Wirespeed
Patent:
9,009,364 →
Application:
14/142,643 →
Method for Storing and Retrieving Packets in High Bandwidth and Low Latency Packet Processing Devices
Patent:
9,736,069 →
Application:
14/142,653 →
Method and Apparatus for Processing of Finite Automata
System and Method for Optimizing Use of Channel State Information
Method and Apparatus for Parallel and Conditional Data Manipulation in a Software-Defined Network Processing Engine
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Method and System for Skipping Over Group(S) of Rules Based on Skip Group Rule
Multi-Rule Approach to Encoding a Group of Rules
Processing Request Keys Based on a Key Size Supported by Underlying Processing Elements
Method and Apparatus for Compiling Search Trees for Processing Request Keys Based on a Key Size Supported by Underlying Processing Elements
Methods and Systems for Single Instruction Multiple Data Programmable Packet Parsers
Application:
14/150,602 →
Publication:
US 2015/0195383
Packet Parsing Engine
Methods and Systems for Distribution of Packets Among Parsing Clusters
Methods and Systems for Resource Management in a Single Instruction Multiple Data Packet Parsing Cluster
Methods and Systems for Flexible Packet Classification
Application:
14/150,657 →
Publication:
US 2015/0195387
Floating Mask Generation for Network Packet Flow
Condition Code Approach for Comparing Rule and Packet Data That Are Provided in Portions
Systems and Methods for Specifying. Modeling, Implementing and Verifying Ic Design Protocols
Block Mask Register Key Processing by Compiling Data Structures to Traverse Rules and Creating a New Rule Set
Method and Apparatus for Managing Write Back Cache
Method and System for Managing Storage Reservation
Patent:
9,454,305 →
Application:
14/165,100 →
Method and System for Communication in a Virtual Machine Environment
Patent:
9,378,036 →
Application:
14/166,082 →
Method And Apparatus For Optimizing Finite Automata Processing
Finite Automata Processing Based on a Top of Stack (TOS) Memory
Method and an Apparatus for Work Packet Queuing, Scheduling, and Ordering with Conflict Queuing
Application:
14/170,955 →
Publication:
US 2015/0220872
Method and an Apparatus for Work Request Arbitration in a Network Processor
Method and an Apparatus for Pre-Fetching and Processing Work for Procesor Cores in a Network Processor
Multiple Ethernet Ports and Port Types Using a Shared Data Path
System and Method to Traverse a Non-Deterministic Finite Automata (NFA) Graph Generated for Regular Expression Patterns with Advanced Features
Generating a Non-Deterministic Finite Automata (NFA) Graph for Regular Expression Patterns with Advanced Features
Method and Apparatus for Memory Access Management
Cdr Voter with Improved Frequency Offset Tolerance
Method and System for Port Trunking
Patent:
9,588,920 →
Application:
14/193,658 →
Partitioned Error Code Computation
Packet Output Processing
Method And Apparatus For Power Gating Hardware Components In A Chip Device
Packet Scheduling in a Network Processor
Packet Shaping in a Network Processor
System on Chip Link Layer Protocol
Apparatus and Method for Processing Alternately Configured Longest Prefix Match Tables
Scannable Flop with a Single Storage Element
Multi-Core Network Processor Interconnect with Multi-Node Connection
Application:
14/201,507 →
Publication:
US 2015/0254182
Inter-Chip Interconnect Protocol for a Multi-Chip System
Method and System for Work Scheduling in a Multi-Chip System
Method and System for Ordering I/O Access in a Multi-Node Environment
Method and Apparatus for Memory Allocation in a Multi-Node System
Apparatus and Method for Table Search with Centralized Memory Pool in a Network Switch
Method and Apparatus for Low Latency Exchange of Data Between a Processor and Coprocessor
Application:
14/204,374 →
Publication:
US 2015/0261535
Merging Independent Writes, Separating Dependent And Independent Writes, And Error Roll Back
NSP Manager
Multiplexer Flop
Work Migration in a Processor
Method and System for Operating System Recovery from a Network Device Including User Selectable Options for Storing an Os Image in Local Storage of a Caching Device
Patent:
9,384,008 →
Application:
14/230,768 →
Compilation of Finite Automata Based on Memory Hierarchy
Processing Of Finite Automata Based On Memory Hierarchy
Memory Management for Finite Automata Processing
Processing of Finite Automata Based on a Node Cache
Method and System for Virtual Machine Communication
Patent:
9,483,290 →
Application:
14/264,927 →
Systems and Methods for Managing Direct Memory Access Operations
Patent:
9,229,893 →
Application:
14/264,957 →
Systems and Methods for Nvme Controller Virtualization to Support Multiple Virtual Machines Running on a Host
System and Method for Automated Functional Coverage Generation and Management for Ic Design Protocols
Method and Apparatus for Analytics in a Network Switch
Method and Apparatus for Table Aging in a Network Switch
Systems and Methods for Cloud-Based Web Service Security Management Basedon Hardware Security Module
Application:
14/299,739 →
Publication:
US 2016/0149877
Systems and Methods for Enabling Access to Extensible Storage Devices Over a Network as Local Storage via Nvme Controller
Counter with Overflow Fifo and a Method Thereof
Application:
14/302,343 →
Publication:
US 2015/0365339
Hierarchical Statistically Multiplexed Counters and a Method Therof
Methods and Systems for Automatically Adding Intelligent Storage Adapters to a Cluster
Patent:
9,423,980 →
Application:
14/302,706 →
Method of Modifying Packets to a Generic Format for Enabling Programmable Modifications and an Apparatus Thereof
Method of Representing a Generic Format Header Using Continuous Bytes and an Apparatus Thereof
Method of Using a Unique Packet Identifier to Identify Structure of a Packet and an Apparatus Thereof
Method of Using Generic Modification Instructions to Enable Flexible Modifications of Packets and an Apparatus Thereof
Method of Using Bit Vectors to Allow Expansion and Collapse of Header Layers Within Packets for Enabling Flexible Modifications and an Apparatus Thereof
Method of Splitting a Packet into Individual Layers for Modification and Intelligently Stitching Layers Back Together After Modification and an Apparatus Thereof
Leaky Bucket Model to Mimic Behavior of a Mac and a Method Thereof
Application:
14/309,700 →
Publication:
US 2015/0372926
Method of Extracting Data from Packets and an Apparatus Thereof
Method of Forming a Hash Input from Packet Contents and an Apparatus Thereof
Method of Handling Large Protocol Layers for Configurable Extraction of Layer Information and an Apparatus Thereof
Method of Reducing Latency in a Flexible Parser and an Apparatus Thereof
Method of Dynamically Renumbering Ports and an Apparatus Thereof
Method of Identifying Internal Destinations of Network Packets and an Apparatus Thereof
Methods and Systems for Processing Task Management Functions in a Cluster Having an Intelligent Storage Adapter
Patent:
9,436,654 →
Application:
14/312,130 →
Systems and Methods for Enabling Local Caching for Remote Storage Devices Over a Network via Nvme Controller
Application:
14/317,467 →
Publication:
US 2015/0317091
Intelligent Graph Walking
Application:
14/324,682 →
Publication:
US 2014/0324900
Engine Architecture for Processing Finite Automata
Managing Instruction Order in a Processor Pipeline
Application:
14/328,923 →
Publication:
US 2016/0011877
Managing Instruction Order in a Processor Pipeline
Application:
14/328,951 →
Publication:
US 2016/0011876
Video Encoder Bit Estimator for Macroblock Encoding
Network Device, System and Method Having a Rotated Chip Floorplan
Application:
14/331,099 →
Publication:
US 2016/0014885
Baseboard Interconnection Device, System and Method
Content Search Mechanism That Uses A Deterministic Finite Automata (DFA) Graph, A DFA State Machine, And A Walker Process
Methods and Systems for Using an Intelligent Storage Adapter for Replication in a Clustered Environment
Patent:
9,477,424 →
Application:
14/339,086 →
Secure Software and Hardware Association Technique
Method and an Apparatus for Co-Processor Data Plane Virtualization
Method and Apparatus for a Virtual System on Chip
Method and Apparatus for a Virtual System on Chip
Methods and Systems for Improved Caching with Data Recovery
Patent:
9,477,414 →
Application:
14/464,535 →
System and Method to Provide Non-Coherent Access to a Coherent Memory System
Methods and Systems for Performing a Read Ahead Operation Using an Intelligent Storage Adapter
Patent:
9,311,021 →
Application:
14/470,309 →
Methods and Systems for Improved Data Caching in a Virtualized Environment
Patent:
9,330,010 →
Application:
14/470,337 →
Method and System for Processing Published Content on the Internet
Systems and Methods for Enabling Value Added Services for Extensible Storage Devices Over a Network via Nvme Controller
Application:
14/473,111 →
Publication:
US 2015/0317176
Method and System for Transmitting Information in a Network
Patent:
9,936,003 →
Application:
14/473,524 →
Low Latency Rate Control System and Method
Method And Apparatus For Power Control
Word Boundary Lock
Method and Apparatus for Improving Data Integrity Using Compressed Soft Information
Method and Apparatus for Quantizing Soft Information Using Non-Linear LLR Quantization
Method and Apparatus for Quantizing Soft Information Using Linear Quantization
Hierarchical Hardware Linked List Approach for Multicast Replication Engine in a Network Asic
Fast Hardware Switchover in a Control Path in a Network Asic
Session Based Packet Mirroring in a Network Asic
Multicast Replication Engine of a Network Asic and Methods Thereof
Methods and Systems for Efficient Cache Mirroring
Patent:
9,460,017 →
Application:
14/498,580 →
Flexible Instruction Execution in a Processor Pipeline
Flexible Instruction Execution in a Processor Pipeline
Traversal With Arc Configuration Information
Apparatus and a Method of Detecting Errors on Registers
Two Modes of a Configuration Interface of a Network Asic
Smart Holding Registers to Enable Multiple Register Accesses
Multiple-Interrupt Propagation Scheme in a Network Asic
Methods and Systems for a Multi-Function Adapter
Patent:
9,936,021 →
Application:
14/530,388 →
Hybrid Wildcard Match Table
Systems and Methods for Supporting Migration of Virtual Machines Accessing Remote Storage Devices Over Network via Nvme Controllers
Adder Decoder
Programmable Validation of Transaction Requests
Programmable Ordering and Prefetch
Register Access Control Among Multiple Devices
Arbitrated Access To Resources Among Multiple Devices
Independent Ordering Of Independent Transactions
Application:
14/540,656 →
Publication:
US 2016/0139806
Apparatus and Method for Scalable and Flexible Table Search in a Network Switch
Apparatus and Method for Fast Search Table Update in a Network Switch
Translation Lookaside Buffer Management
Caching Tlb Translations Using a Unified Page Table Walker Cache
Distributed Interrupt Scheme in a Multi-Processor System
Translation Lookaside Buffer Invalidation Suppression
Distributed Timer Subsystem
Filtering Translation Lookaside Buffer Invalidations
Instruction Cache Translation Management
Application:
14/541,826 →
Publication:
US 2016/0140042
Apparatus and Method for Distributed Instruction Trace in a Processor System
Managing History Information for Branch Prediction
Managing Buffered Communication Between Sockets
Bypass Fifo for Multiple Virtual Channels
Managing Skew in Data Signals
Debug Interface for Multiple Cpu Cores
Testing Semiconductor Devices
Frequency Division Clock Alignment
Controlled Multi-Step De-Alignment of Clocks
Distributed Timer Subsystem Across Multiple Devices
Managing Buffered Communication Between Cores
Instruction Ordering for in-Progress Operations
Controlled Dynamic De-Alignment of Clocks
Managing Skew in Data Signals with Multiple Modes
Frequency Division Clock Alignment Using Pattern Selection
Method and Apparatus for Performing a Weighted Queue Scheduling Using a Set of Fairness Factors
Packet Scheduling Using Hierarchical Scheduling Process
Apparatus and Method for a Multi-Entity Secure Software Transfer
Packet Scheduling Using Hierarchical Scheduling Process with Priority Propagation
Network Switching with Co-Resident Data-Plane and Network Interface Controllers
Management of an Over-Subscribed Shared Buffer
Method and System for Improved Load Balancing of Received Network Traffic
Methods and Systems for Efficient Data Transmission in a Data Center by Reducing Transport Layer Processing
Patent:
9,674,303 →
Application:
14/548,040 →
Packet Classification
Network Switching with Layer 2 Switch Coupled Co-Resident Data-Plane and Network Interface Controllers
Phased Bucket Pre-Fetch in a Network Processor
Methods and Systems for Parallel Distributed Computation
Patent:
9,396,023 →
Application:
14/585,761 →
Method And Apparatus For Managing Processing Thread Migration Between Clusters Within A Processor
Methods and Systems for Efficient Caching Using an Intelligent Storage Adapter
Patent:
9,483,207 →
Application:
14/593,898 →
Methods and Systems for Direct Memory Access Operations
Patent:
9,952,979 →
Application:
14/597,030 →
On-Chip Memory (OCM) Physical Bank Parallelism
Application:
14/604,975 →
Publication:
US 2015/0143060
Method to Measure Edge-Rate Timing Penalty of Digital Integrated Circuits
Methods and Systems for Controlling Transmission Rates in Networks
Patent:
9,426,084 →
Application:
14/609,945 →
High Performance Shifter Circuit
Testbench Builder, System, Device and Method Including a Generic Driver and Transporter
Application:
14/617,522 →
Publication:
US 2016/0139204
Testbench Builder, System, Device and Method
Testbench Builder, System, Device and Method Including a Dispatcher
Testbench Builder, System, Device and Method Including a Generic Monitor and Transporter
Testbench Builder, System, Device and Method Having Agent Loopback Functionality
Dram Address Protection
Apparatus and Method for Software Enabled Access to Protected Hardware Resources
Methods and Systems for Network Devices and Associated Network Transmissions
Patent:
9,590,897 →
Application:
14/632,200 →
Anchored Patterns
Automated Flip-Flop Insertions in Physical Design Without Perturbation of Routing
Communication and Control Topology for Efficient Testing of Sets of Devices
Managing Reuse Information for Memory Pages
Application:
14/637,579 →
Publication:
US 2016/0259732
Managing Reuse Information with Multiple Translation Stages
Managing Reuse Information in Caches
Multi-Function Delay Locked Loop
Network Device Scheduler and Methods Thereof
Patent:
9,590,924 →
Application:
14/658,544 →
Lookup Cluster Complex
Systems and Methods for Secured Hardware Security Module Communication with Web Service Hosts
Application:
14/662,012 →
Publication:
US 2015/0358294
Managing Address-Independent Page Attributes
Methods and Systems for Reliable Network Communication
Patent:
9,692,560 →
Application:
14/663,912 →
Repeater Insertions Providing Reduced Routing Perturbation Caused by Flip-Flop Insertions
Systems and Methods for Secured Key Management via Hardware Security Module for Cloud-Based Web Services
Application:
14/667,238 →
Publication:
US 2015/0358311
Methods and Systems for Accessing Storage Using a Network Interface Card
Packet Processor Forwarding Database Cache
Phantom Queue Link Level Load Balancing System, Method and Device
Work Request Processor
Method and Apparatus for Bypass Routing of Multicast Data Packets and Avoiding Replication to Reduce Overall Switch Latency
Testbench Builder, System, Device and Method with Phase Synchronization
Co-Verification - of Hardware and Software, a Unified Approach in Verification
Patent:
9,372,772 →
Application:
14/671,993 →
Software Assisted Hardware Configuration for Software Defined Network System-On-Chip
Packet Tracking in a Verification Environment
Testbench Builder, System, Device and Method Including Latency Detection
Managing Skew in Data Signals with Adjustable Strobe
Variable Strobe for Alignment of Partially Invisible Data Signals
Patent:
9,349,434 →
Application:
14/672,874 →
Packet Memory System, Method and Device for Preventing Underrun
Packet Processing System, Method and Device to Optimize Packet Buffer Space
Packet Processing System, Method and Device Having Reduced Static Power Consumption
Packet Processing System, Method and Device Utilizing a Port Client Chain
Packet Processing System, Method and Device Utilizing Memory Sharing
Control Path Subsystem, Method and Device Utilizing Memory Sharing
Datapath Subsystem, Method and Device Utilizing Memory Sharing
Identifying Inversion Error in Logic Equivalence Check
Approach for Chip-Level Flop Insertion and Verification Based on Logic Interface Definition
Determination of Flip-Flop Count in Physical Design
Approach for Logic Signal Grouping and Rtl Generation Using Xml
Method and Apparatus for Using Multiple Linked Memory Lists
Parser Engine Programming Tool for Programmable Network Devices
Code Processor to Build Orthogonal Execution Blocks for Programmable Network Devices
Algorithm to Achieve Optimal Layout of Decision Logic Elements for Programmable Network Devices
Algorithm to Derive Logic Expression to Select Execution Blocks for Programmable Network Devices
Algorithm to Achieve Optimal Layout of Instruction Tables for Programmable Network Devices
Code Generator for Programmable Network Devices
Compiler Architecture for Programmable Application Specific Integrated Circuit Based Network Devices
Barrel Compactor System, Method and Device
Barrel Compactor System, Method and Device Having Cell Combination Logic
Policer Architecture
Apparatus and Method for Accelerated Page Link List Processing in a Packet Processor Operating at Wirespeed
Patent:
9,262,369 →
Application:
14/676,791 →
Systems and Methods for Hardware Accelerated Timer Implementation for Openflow Protocol
Methods and Systems for Control Block Routing
Patent:
9,720,733 →
Application:
14/698,581 →
Systems and Methods for Defining Storage
Patent:
10,129,162 →
Application:
14/716,689 →
Systems and Methods for Secured Backup of Hardware Security Modules for Cloud-Based Web Services
Integrated Fabric Adapter and Associated Methods Thereof
Patent:
9,819,515 →
Application:
14/724,273 →
Messaging with Flexible Transmit Ordering
Systems and Methods for Sending and Receiving Information via a Network Device
Patent:
9,401,879 →
Application:
14/747,790 →
Network Devices Having Configurable Receive Packet Queues and Related Methods
Patent:
9,282,000 →
Application:
14/749,964 →
Methods and Systems for Using Shared Logic at Network Devices
Patent:
9,588,839 →
Application:
14/805,161 →
Qos Based Dynamic Execution Engine Selection
Systems and Methods for Secured Communication Hardware Security Module and Network-Enabled Devices
Application:
14/829,233 →
Publication:
US 2015/0358313
Caching Methods and Systems Using a Network Interface Card
Method and Apparatus for Providing a Low Latency Transmission System Using Adjustable Buffers
Local Ordering of Instructions in a Computing System
Reverse Nfa Generation and Processing
Reverse NFA Generation And Processing
Application:
14/863,816 →
Publication:
US 2016/0021123
Switching Methods and Systems for a Network Interface Card
Patent:
9,800,524 →
Application:
14/864,323 →
Systems and Methods for Allowing Flexible Chip Configuration by External Entity While Maintaining Secured Boot Environment
Methods and Systems for Managing Address List Control Blocks
Patent:
9,753,852 →
Application:
14/919,508 →
Scope In Decision Trees
Hybrid Wildcard Match Table
Systems and Methods for Hardware Accelerated Metering for Openflow Protocol
Carry Chain for Simd Operations
Implementing 128-Bit Simd Operations on a 64-Bit Datapath
Method and System for Compressing Data for a Translation Look Aside Buffer (Tlb)
Automatic Data Rate Matching
Approach for Interfacing a Pipeline with Two or More Interfaces in a Processor
Distributing Resource Requests in a Computing System
Sharing Resources in a Multi-Context Computing System
Systems and Methods for Enabling Local Caching for Remote Storage Devices Over a Network via Nvme Controller
Application:
14/941,396 →
Publication:
US 2016/0077740
Methods and Systems for Processing Read and Write Requests
Patent:
9,946,671 →
Application:
14/969,950 →
Voltage-Controlled Oscillator with Improved Tuning Curve Linearization
Patent:
9,673,753 →
Application:
15/000,840 →
Protocol Independent Programmable Switch (Pips) Software Defined Data Center Networks
Managing Translation Invalidation
Managing Synonyms in Virtual-Address Caches
Content Search Pattern Matching Using Deterministic Finite Automata (Dfa) Graphs
Method and Apparatus for Dynamic Virtual System on Chip
Apparatus and Method for Processing Alternately Configured Longest Prefix Match Tables
Edge Rate Control Calibration
Patent:
9,590,797 →
Application:
15/143,282 →
Voltage Regulator with Adaptive Bias Network
System and Method for Rule Matching in a Processor
Methods and Apparatus for Providing Soft and Blind Combining for Pusch Cqi Processing
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Methods and Systems for Securing Data Stored at a Storage Area Network
Patent:
10,129,219 →
Application:
15/169,466 →
Managing Virtual-Address Caches for Multiple Memory Page Sizes
Methods and Systems for Message Logging and Retrieval in Computer Systems
Patent:
10,275,261 →
Application:
15/363,995 →
Fiber Optic Cable Retention and Guide Clip
Patent:
520,863 →
Application:
29/209,313 →
Method and Apparatus for Providing Soft and Blind Combining Techniques for PUSCH Baseband Processing
Application:
62/267,221 →
Method and Apparatus for Providing Programmable Mixed-Radix Dft Processor Using Vector Engines
Application:
62/274,062 →
Method and Apparatus for Dynamically Generating Mixed-Radix Twiddle Coefficient Vectors
Application:
62/274,686 →
Method and Apparatus for Configuring Multiple Sectors with Multiple Radio Frequency Frames
Application:
62/274,709 →
Method and Apparatus for Providing Programmable Mixed-Radix DFT/IDFT Processor Using Vector Memory Subsystem
Application:
62/279,345 →
Method and Apparatus for Providing Fft Engine Using Single Delay Feedback Scheme
Application:
62/288,382 →
Frequency Offset Estimator
Application:
62/335,366 →
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
Change of Name
Dec 14, 2016
From: QLOGIC SWITCH PRODUCTS, INC.
To: QLOGIC SWITCH PRODUCTS, LLC
Reel/Frame 040939/0819 →
Security Agreement
Mar 1, 2017
From: QLOGIC CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 041854/0119 →
Merger
Oct 18, 2017
From: QLOGIC CORPORATION
To: CAVIUM, INC.
Reel/Frame 044812/0504 →
Assignment of Assignor's Interest
Oct 20, 2017
From: QLOGIC SWITCH PRODUCTS, LLC
To: QLOGIC LLC
Reel/Frame 043912/0521 →
Change of Name
Nov 3, 2017
From: QLOGIC CORPORATION
To: QLOGIC LLC
Reel/Frame 044366/0832 →
Merger
Dec 14, 2017
From: QLOGIC CORPORATION
To: CAVIUM, INC.
Reel/Frame 045628/0419 →
Certificate of Conversion and Certificate of Formation
Oct 2, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047185/0422 →
Change of Name
Oct 8, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047205/0953 →
Change of Name
Jan 11, 2019
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 049367/0717 →
Assignment of Assignor's Interest
Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
Assignment of Assignor's Interest
May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →