Translation bypass in multi-stage address translation
View Patent ↗A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Lookups to the caches of the MTLB can be selectively bypassed based on a control configuration and the attributes of a received address.
1. A circuit comprising:
a cache configured to store translations between address domains, the cache addressable as a first logical portion and a second logical portion, the first logical portion configured to store translations between a first address domain and a second address domain, the second logical portion configured to store translations between the second address domain and a third address domain; and
a processor configured to 1) control a bypass of at least one of the first and second logical portions with respect to a translation of an address indicated by an address request, the processor determining whether to activate the bypass based on an attribute of the address indicated by the address request, and 2) match the address request against a non-bypassed portion of the cache in accordance with the bypass and output a corresponding address result.
2. The circuit of claim 1 , wherein the processor is further configured to control the bypass based on whether the address indicated by the address request specifies a subset of a memory excluded from a given address translation.
3. The circuit of claim 1 , wherein the processor is further configured to control the bypass based on whether the address indicated by the address request is a member of a range of addresses excluded from a given address translation.
4. The circuit of claim 1 , wherein the processor is further configured to control the bypass based on an indication of whether an address specified by the address request is mapped to the cache.
5. The circuit of claim 1 , wherein the processor is further configured to control the bypass based on a bypass indication.
6. The circuit of claim 5 , wherein the bypass indication is a component of the address request.
7. The circuit of claim 5 , wherein the bypass indication is a control bit received by the processor.
8. The circuit of claim 1 , wherein the processor is further configured to control the bypass based on 1) an indication of whether an address specified by the address request is mapped to the cache, and 2) a bypass indication with respect to the address request.
9. The circuit of claim 1 , wherein the processor is further configured to transform an address component of the address request.
10. The circuit of claim 9 , wherein transforming the address component includes applying an address mask.
11. The circuit of claim 9 , wherein the processor transforms the address component in place of a lookup of at least one of the first and second logical portions in accordance with the bypass.
12. The circuit of claim 1 , further comprising a register configured to define a boundary between the first and second logical portions.
13. The circuit of claim 12 , wherein the location of the boundary varies according to a value stored at the register.
14. A method of caching address translations in a memory architecture, comprising:
storing translations between a first address domain and a second address domain to a first logical portion of a cache;
storing translations between the second addressing domain and a third address domain to a second logical portion of the cache;
controlling a bypass of at least one of the first and second logical portions with respect to a translation of an address indicated by an address request, the bypass being determined based on an attribute of the address indicated by the address request; and
matching the address request against non-bypassed portion of the cache in accordance with the bypass and outputting a corresponding address result.
15. The method of claim 14 , wherein the bypass is controlled based on whether the address indicated by the address request specifies a subset of a memory excluded from a given address translation.
16. The method of claim 14 , wherein the bypass is controlled based on whether the address indicated by the address request is a member of a range of addresses excluded from a given address translation.
17. The method of claim 14 , wherein the bypass is controlled based on an indication of whether an address specified by the address request is mapped to the cache.
18. The method of claim 14 , wherein the bypass is controlled based on a bypass indication.
19. The method of claim 18 , wherein the bypass indication is a component of the address request.
20. The method of claim 18 , wherein the bypass indication is a control bit independent of the address request.
21. The method of claim 14 , wherein the bypass is controlled based on 1) an indication of whether an address specified by the address request is mapped to the cache, and 2) a bypass indication with respect to the address request.
22. The method of claim 14 , further comprising transforming an address component of the address request.
23. The method of claim 22 , wherein transforming the address component includes applying an address mask.
24. The method of claim 22 , wherein transforming the address component in place of a lookup of at least one of the first and second logical portions in accordance with the bypass.
25. The method of claim 14 , further comprising defining a boundary between the first and second logical portions.
26. The method of claim 25 , wherein the location of the boundary varies according to a value stored at a register.
27. A circuit comprising:
a translation lookaside buffer (TLB) configured to store translations between address domains, the TLB addressable as a guest TLB and a root TLB, the guest TLB configured to store translations between a guest virtual address (GVA) domain and a guest physical address (GPA) domain, the root TLB configured to store translations between the GPA domain and a root physical address (RPA) domain, each entry in the TLB including a bit indicating whether the entry is a member of the guest TLB or the root TLB; and
a processor configured to 1) control a bypass of at least one of guest TLB and root TLB with respect to a translation of an address indicated by an address request, the processor determining whether to activate the bypass based on an attribute of the address indicated by the address request, and 2) match the address request against a non-bypassed portion of the cache in accordance with the bypass and output a corresponding address result.
28. The circuit of claim 27 , further comprising a register configured to define a boundary between the guest TLB and the root TLB.