METHOD AND APPARATUS FOR LOW LATENCY EXCHANGE OF DATA BETWEEN A PROCESSOR AND COPROCESSOR
According to at least one example embodiment, a method of processing a wide command includes storing wide command data in a first physical structure of a processor. Information associated with the wide command is determined based on the wide command data and/or a corresponding memory address range associated with the wide command. The information associated with the wide command determined includes a size of the wide command and is stored in a second physical structure of the processor. The processor causes the wide command data and the information associated with the wide command to be provided directly to a coprocessor for executing the wide command. The processor and the coprocessor may reside on a single chip device. Alternatively, the processor and the coprocessor may reside on separate chip devices in a multi-chip system.
1 . A method of processing a wide command comprising:
storing wide command data in a first physical structure of a processor;
determining information associated with the wide command based on the wide command data or a corresponding memory address range associated with the first physical structure of the processor, the information determined including a size of the wide command;
storing the information determined in a second physical structure of the processor; and
causing the first physical structure and the second physical structure to provide the wide command data and the information associated with the wide command directly to a coprocessor for executing the wide command.
2 . The method as recited in claim 1 further comprising executing the wide command by the coprocessor.
3 . The method as recited in claim 2 further comprising providing a response to the processor by the coprocessor upon executing the wide command, the response being stored in a third physical structure of the processor.
4 . The method as recited in claim 3 further comprising:
storing in the third physical structure an indication of no response prior to storing the information associated with the wide command in the second physical structure; and
overwriting the indication of no response with an indication of a complete response upon the response being completely stored in the third structure, access to the response being provided only after the indication of no response is overwritten with the indication of a complete response.
5 . The method as recited in claim 3 further comprising preventing, by the processor, access to any address of the third physical structure associated with the response before the response is completely stored in the third structure.
6 . The method as recited in claim 3 further comprising:
implementing a synchronization operation by the processor;
preventing, by the processor, the synchronization operation and any subsequent operations from executing before the response is completely stored in the third physical structure.
7 . The method as recited in claim 3 further comprising:
providing, by the processor, an indication of a status of the wide command; and
providing access to a memory address associated with the response in the third physical structure only if the indication of the status indicates that the wide command is completed.
8 . The method as recited in claim 1 , wherein the information associated with the wide command further includes an address referencing the coprocessor.
9 . The method as recited in claim 8 , wherein the information associated with the wide command further includes a size of a response and an address of a third physical structure for storing the response in the processor.
10 . The method as recited in claim 1 , wherein the first physical structure includes at least one of a write buffer and a dedicated physical structure.
11 . The method as recited in claim 1 , wherein the processor and the coprocessor reside in a single chip device.
12 . The method as recited in claim 1 , wherein the processor and the coprocessor reside in different chip devices of a the multi-chip system.
13 . An apparatus comprising:
a coprocessor; and
a processor including a first physical structure and a second physical structure, the processor configured to:
store wide command data in the first physical structure of a processor;
determine information associated with the wide command based on the wide command data or a corresponding memory address range associated with the first physical structure of the processor, the information determined including a size of the wide command;
store the information determined in the second physical structure of the processor; and
cause the first physical structure and the second physical structure to provide the wide command data and the information associated with the wide command directly to the coprocessor for executing the wide command.
14 . The apparatus as recited in claim 13 , wherein the coprocessor is configured to execute the wide command.
15 . The apparatus as recited in claim 14 , wherein the coprocessor is further configured to provide a response to the processor upon executing the wide command, the processor further including a third physical structure and further configured to store the response in the third physical structure.
16 . The apparatus as recited in claim 15 , wherein the processor is further configured to:
store in the third physical structure an indication of no response prior to storing the information associated with the wide command in the second physical structure; and
overwrite the indication of no response with an indication of a complete response upon the response being completely stored in the third structure, access to the response provided only after the indication of no response is overwritten with the indication of a complete response.
17 . The apparatus as recited in claim 15 , wherein the processor is further configured to prevent access to any address of the third physical structure associated with the response before the response is completely stored in the third structure.
18 . The apparatus as recited in claim 15 , wherein the processor is further configured to:
implement a synchronization operation;
prevent the synchronization operation and any subsequent operations from executing before the response is completely stored in the third physical structure.
19 . The apparatus as recited in claim 15 , wherein the processor is further configured to:
provide an indication of a status of the wide command; and
provide access to a memory address associated with the response in the third physical structure only if the indication of the status indicates that the wide command is completed.
20 . The apparatus as recited in claim 13 , wherein the information associated with the wide command further includes an address referencing the coprocessor.
21 . The apparatus as recited in claim 20 , wherein the information associated with the wide command further includes a size of a response and an address of a third physical structure for storing the response in the processor.
22 . The apparatus as recited in claim 13 , wherein the first physical structure includes at least one of a write buffer and a dedicated physical structure.
23 . The apparatus as recited in claim 13 , wherein the apparatus is a chip device.
24 . The apparatus as recited in claim 13 , wherein the apparatus is a multi-chip system including multiple chip devices.
25 . The apparatus as recited in claim 24 , wherein the processor and the coprocessor reside in different chip devices, of the multiple chip devices, in the multi-chip system.