IP Library Granted Patent US 9,311,268
Granted Patent B1
US 9,311,268 · App. 14/058,887 · Granted Apr 12, 2016

Method and system for communication with peripheral devices

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Quick Facts
Patent No.
US 9,311,268
App. No.
14/058,887
Granted
Apr 12, 2016
Kind
B1
Abstract

Methods and systems for ignoring protocol defined framing errors at a peripheral device coupled to a processor via an interconnect system are provided. When a framing error violation does not affect data transfer to the peripheral device or from the peripheral device, the protocol defined link training sequence is disabled to ignore the framing error and the peripheral device continues to process data regardless of the framing error.

Claims (27)

1. A machine implemented method for ignoring protocol defined framing error at a peripheral device coupled to a processor via an interconnect system, comprising:

when a framing error violation does not affect data transfer to the peripheral device or from the peripheral device, disabling protocol defined link training sequence to ignore the framing error; and

continue processing data by the peripheral device regardless of the framing error.

2. The method of claim 1 , wherein the interconnect system is a PCI-Express link.

3. The method of claim 1 , wherein the peripheral device is an adapter coupled to the processor via a PCI-Express link.

4. The method of claim 1 , wherein the peripheral device is a network adapter.

5. The method of claim 1 , wherein the peripheral device is a host bus adapter.

6. The method of claim 1 , wherein the peripheral device is a converged network adapter that can process both storage and network traffic.

7. The method of claim 1 , wherein the peripheral device detects the framing error and uses a pre-loaded data structure for instructions to ignore the framing error.

8. A machine implemented method for ignoring protocol defined framing error at a peripheral device coupled to a processor via an interconnect system, comprising:

maintaining a data structure at a memory device for storing instructions to ignore a certain framing error violation that does not affect data transfer to the peripheral device or from the peripheral device;

disabling a protocol defined link training sequence to ignore the framing error; and

continue processing data by the peripheral device regardless of the framing error.

9. The method of claim 8 , wherein the interconnect system is a PCI-Express link.

10. The method of claim 8 , wherein the peripheral device is an adapter coupled to the processor via a PCI-Express link.

11. The method of claim 8 , wherein the peripheral device is a network adapter.

12. The method of claim 8 , wherein the peripheral device is a host bus adapter.

13. The method of claim 8 , wherein the peripheral device is a converged network adapter that can process both storage and network traffic.

14. A peripheral device, comprising:

a host interface communicating with a processor of a computing device via an interconnect system; and

a memory device for storing instructions to ignore a framing error violation that does not affect data transfer to the peripheral device or from the peripheral device; disable a protocol defined link training sequence to ignore the framing error; and continue processing data regardless of the framing error.

15. The peripheral device of claim 14 , wherein the interconnect system is a PCI-Express link.

16. The peripheral device of claim 14 , wherein the peripheral device is an adapter coupled to the processor via a PCI-Express link.

17. The peripheral device of claim 14 , wherein the peripheral device is a network adapter.

18. The peripheral device of claim 14 , wherein the peripheral device is a host bus adapter.

19. The peripheral device of claim 14 , wherein the peripheral device is a converged network adapter that can process both storage and network traffic.

20. The peripheral device of claim 14 wherein the instructions are stored in a pre-loaded data structure.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CHANGE OF NAME Recorded Oct 8, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047205/0953 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
MERGER Recorded Oct 18, 2017
From: QLOGIC CORPORATION
To: CAVIUM, INC.
Reel/Frame 044812/0504 →
SECURITY AGREEMENT Recorded Mar 1, 2017
From: QLOGIC CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 041854/0119 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2013
From: CHEN, QIAN; WEIMER, RONALD A.
To: QLOGIC, CORPORATION
Reel/Frame 031445/0270 →