IP Library Granted Patent US 8,831,108
Granted Patent B2
US 8,831,108 · App. 13/067,051 · Granted Sep 9, 2014

Low latency rate control system and method

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Quick Facts
Patent No.
US 8,831,108
App. No.
13/067,051
Granted
Sep 9, 2014
Kind
B2
Abstract

An encoder within a video transmission system controls the bit allocation at a sub-frame level. A frame is divided into smaller blocks, known as rate control blocks. Rate control blocks are used as the basic unit for bit allocation. This bit allocation achieves the target bit rate desired by the system as well as meet latency constraints. The encoder uses the slice partitioning capabilities to generate the rate control blocks using one or more slices of the image frame. This feature allows the decoder to decode the rate control blocks independently and ensures that the encoded data size for each rate control block is allocated. The encoder also detects the overflow condition for the buffer and performing an operation to avoid the overflow condition based on whether the image frame is an inter-frame or a intra-frame.

Claims (11)

1. A method for encoding an image frame within a video transmission system, the method comprising:

selecting a rate control block of the image frame, wherein the rate control block includes a plurality of macroblocks;

determining a rate control block bit rate;

designating a buffer size to correspond to the size of the rate control block;

encoding the plurality of macroblocks of the rate control block according to the bit rate; and

avoiding overflow of the buffer by alternately skipping encoding for selected inter-frame macroblocks of the rate control block and removing prediction residue from intra-frame macroblocks of the rate control block.

2. The method of claim 1 , wherein the determining step includes setting the bit rate to correspond to a size of the rate control block.

3. The method of claim 1 , further comprising partitioning the image frame into a plurality of rate control blocks.

4. The method of claim 1 , further comprising performing macroblock level rate control.

5. The method of claim 4 , further comprising determining whether the buffer is in an overflow state due to a size of the encoded plurality of macroblocks.

6. The method of claim 4 , wherein the performing macroblock level rate control includes replicating a macroblock of a previous frame.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CHANGE OF NAME Recorded Jan 11, 2019
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 049367/0717 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
SECURITY AGREEMENT Recorded Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2011
From: DUENAS, ALBERTO; IZQUIERDO, FRANCISCO RONCERO; GARCIA, GORKA
To: CAVIUM, INC.
Reel/Frame 026625/0680 →