Differential amplifier with duty cycle compensation
View Patent ↗A differential amplifier replicates the input stage and cross-connects the inputs, so that the input-to-output delay will be balanced in an averaged sense. The outputs of each of the two input stages are then summed after an open loop delay matched inversion has taken place. The result is a reduction in the duty cycle distortion of the receiver amplifier over process voltage and temperature (PVT) variation. This is enabled by the fact that a full swing CMOS delay cell can be made to have good delay matching over PVT, whereas the input stage to a differential amplifier may, depending on architecture, have poor delay matching because of impedance mismatches within the amplifier.
1. A circuit comprising:
a first differential amplifier having a positive input, a negative input and an output;
a second differential amplifier having a positive input, a negative input and an output, the positive input and negative input of the second differential amplifier cross-connected with the negative input and positive input of the first differential amplifier;
a first buffer having an input and an output, the input coupled to the output of the first differential amplifier;
a second buffer having an inverted input and an output, the inverted input coupled to the output of the second differential amplifier, the first buffer and the second buffer having matched delays;
a summer having first and second positive inputs and an output, the first positive input coupled to the output of the first buffer and the second positive input coupled to the output of the second buffer.
2. The circuit of claim 1 , wherein the matched delays include variable delay elements that are adaptable to variation in process, voltage and temperature.
3. The circuit of claim 2 , wherein the variable delay elements are adjustable by a programmable control input, the control input having one of an analog or a digital value.
4. The circuit of claim 2 , wherein the variable delay elements are adjustable by configuring at least one fuse.
5. The circuit of claim 2 , wherein the delay elements are adjusted in response to an output of a phase detector comparing outputs of the matched delays.
6. The circuit of claim 1 , wherein the matched delays include delay elements comprising lumped passive elements.
7. The circuit of claim 6 , wherein the matched delays further include at least one buffer configured between the lumped passive elements and the output of the matched delays.
8. The circuit of claim 1 , wherein the matched delays include delay elements comprising distributed passive elements.
9. The circuit of claim 8 , wherein the matched delays further include at least one buffer configured between the distributed passive elements and the output of the matched delays.
10. The circuit of claim 1 , wherein the matched delays include bipolar delay elements.
11. The circuit of claim 1 , further comprising a phase detector configured to receive and compare phases of the outputs of the first and second differential amplifiers, the first and second differential amplifiers adjusting respective output delays based on an output of the phase detector.
12. A circuit comprising:
a first input stage comprising a first differential amplifier having differential inputs and a single-ended output, and a first buffer having an input and an output, the output of the first differential amplifier coupled to the input of the first buffer;
a second input stage comprising a second differential amplifier having differential inputs and a single-ended output, and a second buffer having an inverted input and an output, the output of the second differential amplifier coupled to the inverter input of the second buffer, where the differential inputs of the first differential amplifier and the differential inputs of the second differential amplifier are cross-connected;
a summer having first and second positive inputs and an output, the first positive input coupled to the output of the first buffer and the second positive input coupled to the output of the second buffer.