Systems and methods for managing direct memory access operations
View Patent ↗Methods and systems for DMA operations are provided. A plurality of control blocks are stored at a memory of a receive module of a device coupled to a computing device, where the control blocks store information regarding data packets stored at a receive buffer accessible to the receive module. At least a first control block and a second control block are retrieved from the memory; and a first DMA register set is assigned to the first control block and a second DMA register set is assigned to the second control block. The first control block and the second control block are simultaneously pre-processed to configure the first DMA register set and the second DMA register set.
1. A machine implemented method, comprising:
storing a plurality of control blocks at a memory of a receive module of a device coupled to a computing device, where the control blocks store information regarding data packets stored at a receive buffer accessible to the receive module; wherein the device includes a plurality of processing modules and a memory interface that manages a local memory for storing information regarding the plurality of control blocks;
retrieving at least a first control block and a second control block from the memory;
assigning a first direct memory access (DMA) register set to the first control block and a second DMA register set to the second control block;
simultaneously pre-processing the first control block and the second control block to configure the first DMA register set and the second DMA register set;
starting a first DMA operation for the first control block, while configuring the second DMA register set; and
starting a DMA operation for the second control block, immediately after DMA operations for the first control block are completed;
wherein pre-processing of a control block is based on an operation type and includes:
determining if data is to be moved to a specific host address, at least one anonymous buffer, or an address list;
requesting a buffer pool based on the determination; and
setting up an appropriate register set pair.
2. The method of claim 1 , wherein the first control block includes a plurality of DMA requests that are different from a number of DMA requests for the second control block.
3. The method of claim 1 , wherein the device is an adapter for processing input/output requests for accessing data stored in a storage area network.
4. The method of claim 1 , wherein the pre-processing of the first control block and the second control block is based on a control block type.
5. The method of claim 4 , wherein the control block type is to place data at anonymous host memory location.
6. The method of claim 4 , wherein the control block type is to send a completion message.
7. The method of claim 4 , wherein the control block is for sending data based on an address list.
8. A non-transitory, machine readable storage medium storing executable instructions, which when executed by a machine, causes the machine to perform a method, the method:
storing a plurality of control blocks at a memory of a receive module of a device coupled to a computing device, where the control blocks store information regarding data packets stored at a receive buffer accessible to the receive module; wherein the device includes a plurality of processing modules and a memory interface that manages a local memory for storing information regarding the plurality of control blocks;
retrieving at least a first control block and a second control from the memory;
assigning a first direct memory access (DMA) register set to the first control block and a second (DMA) register set to the second control block;
simultaneously pre-processing the first control block and the second control block to configure the first DMA register set and the second DMA register set;
starting a first DMA operation for the first control block, while the second DMA register set is ready for starting a DMA operation for the second control block, immediately after DMA operations for the first control block are completed;
wherein pre-processing of a control block is based on an operation type and includes:
determining if data is to be moved to a specific host address, at least one anonymous buffer, or an address list;
requesting a buffer pool based on the determination; and
setting up an appropriate register set pair.
9. The storage medium of claim 8 , wherein the first control block includes a plurality of DMA requests that are different from a number of DMA requests for the second control block.
10. The storage medium of claim 8 , wherein the device is an adapter for processing input/output requests for accessing data stored in a storage area network.
11. The storage medium of claim 8 , wherein the pre-processing of the first control block and the second control block is based on a control block type.
12. The storage medium of claim 11 , wherein the control block type is to place data at anonymous host memory location.
13. The storage medium of claim 11 , wherein the control block type is to send a completion message.
14. The storage medium of claim 11 , wherein the control block is for sending data based on an address list.
15. A system, comprising:
a receive module of a device, executing instructions for:
storing a plurality of control blocks at a memory, where the control blocks store information regarding data packets stored at a receive buffer accessible to the receive module;
retrieving at least a first control block and a second control from the memory;
assigning a first direct memory access (DMA) register set to the first control block and a second (DMA) register set to the second control block;
simultaneously pre-processing the first control block and the second control block to configure the first DMA register set and the second DMA register set; and
starting a first DMA operation for the first control block, while the second DMA register set is ready for starting a DMA operation for the second control block, immediately after DMA operations for the first control block are completed;
wherein pre-processing of a control block is based on an operation type and includes:
determining if data is to be moved to a specific host address, at least one anonymous buffer, or an address list;
requesting a buffer pool based on the determination; and
setting up an appropriate register set pair.
16. The system of claim 15 , wherein the first control block includes a plurality of DMA requests that are different from a number of DMA requests for the second control block.
17. The system of claim 15 , wherein the device is an adapter for processing input/output requests for accessing data stored in a storage area network.
18. The system of claim 15 , wherein the pre-processing of the first control block and the second control block is based on a control block type.
19. The system of claim 18 , wherein the control block type is to place data at anonymous host memory location.
20. The system of claim 18 , wherein the control block type is to send a completion message.
21. The system of claim 15 , wherein the device includes a plurality of processing modules and a memory interface that manages a local memory for storing information regarding the plurality of control blocks.