Direct hardware processing of internal data structure fields
View Patent ↗In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.
1. A data processing apparatus comprising:
a template storage unit storing a template having a plurality of entries, each template entry corresponding to an internal field of a data structure, each template entry specifying a memory address offset of a word relative to a base address of the data structure, and an internal field bitspan within the word, the field bitspan defining a field start position and a field length, the field bitspan being bounded by at least one intra-byte bit not forming a byte boundary;
a base register storing the base address of the data structure;
a target register;
a control unit connected to the template storage unit and an instruction memory, comprising logic configured to
receive from the instruction memory a machine language memory access instruction including an identifier of the base register and an identifier of a target template entry, the target template entry corresponding to a target field of the data structure, and
transmit to the template storage unit the identifier of the target template entry;
an internal-field address arithmetic logic unit connected to the base register, the template storage unit, and a data memory, comprising logic configured to
receive the base memory address from the base register;
receive a target memory address offset for the target field from the template storage unit,
determine an address of the target field by adding the base memory address and target memory address offset; and
transmit to the data memory a memory access command identifying the target memory address offset; and
an intra-word processing arithmetic logic unit connected to the target register and the data memory, comprising logic configured to perform an intra-word content modification operation as at least part of a content of the word is transferred between the data memory and the target register.
2. The apparatus of claim 1 , wherein the internal-field memory access instruction is a load instruction.
3. The apparatus of claim 2 , wherein the load instruction is a load-and-extract instruction.
4. The apparatus of claim 2 , wherein the load instruction is a load-extract-and-sign instruction.
5. The apparatus of claim 2 , wherein the load instruction is a masked-load instruction.
6. The apparatus of claim 1 , wherein the internal-field memory access instruction is a store instruction.
7. The apparatus of claim 6 , wherein the store instruction is a masked-store instruction.
8. The apparatus of claim 1 , wherein the intra-word content modification operation comprises an extraction of the internal field.
9. The apparatus of claim 1 , wherein the intra-word content modification operation comprises an extraction of the internal field and an addition of at least one sign bit.
10. The apparatus of claim 1 , wherein the intra-word content modification operation comprises masking a bitspan of the internal field within the word.
11. A data processing method comprising:
receiving an internal-field memory access machine code instruction for an internal field of a data structure, the internal-field memory access machine code instruction including an identifier of a base register and an identifier of a target template entry, wherein
the internal field occupies an internal field bitspan within a target word, the field bitspan defining a field start position and a field length, the field bitspan being bounded by at least one intra-byte bit not forming a byte boundary,
the target word is distinct from a base word for the data structure,
the base register stores a base memory address for the data structure, and
the template entry specifies a memory address offset of the target word relative to the base memory address, and the internal field bitspan; and
executing the internal-field memory access machine code instruction, wherein executing the internal-field memory access machine code instruction comprises
determining an address of the target field by adding the base memory address and memory address offset, and
performing an intra-word content modification operation as at least part of a content of the word is transferred between a memory and a data register.
12. The method of claim 11 , wherein the internal-field memory access instruction is a load instruction.
13. The method of claim 12 , wherein the load instruction is a load-and-extract instruction.
14. The method of claim 12 , wherein the load instruction is a load-extract-and-sign instruction.
15. The method of claim 12 , wherein the load instruction is a masked-load instruction.
16. The method of claim 11 , wherein the internal-field memory access instruction is a store instruction.
17. The method of claim 16 , wherein the store instruction is a masked-store instruction.
18. The method of claim 11 , wherein the intra-word content modification operation comprises an extraction of the internal field.
19. The method of claim 11 , wherein the intra-word content modification operation comprises an extraction of the internal field and an addition of at least one sign bit.
20. The method of claim 11 , wherein the intra-word content modification operation comprises masking a bitspan of the internal field within the word.