Method and system for communication using multiple DMA channels
View Patent ↗Method and system for sending data from a memory of a computing system interfacing with a device is provided. An input/output control block (IOCB) from the computing system for transferring the data from the memory of the computing system is received by the device. The device then allocates a plurality of DMA channels to the IOCB for transferring the data from the memory of the computing system when a number of pending input/output (I/O) requests when the IOCB is received is less than a number of available direct memory access (DMA) channels to receive the data from the memory of the computing system.
1. A machine implemented method for sending data from a memory of a computing system interfacing with a device, comprising:
receiving an input/output control block (IOCB) from the computing system for transferring the data from the memory of the computing system to the device;
allocating a plurality of DMA channels to the IOCB for transferring the data from the memory of the computing system when a number of pending input/output (I/O) requests when the IOCB is received is less than a number of available direct memory access (DMA) channels to receive the data from the memory of the computing system;
receiving portions of the data from the memory of the computing system and saving the portions of data at one or more memory storage locations at the device;
tracking an order in which the portions of data for the IOCB are received compared to any other pending request; and
transmitting the data to another device via a link.
2. The method of claim 1 , wherein the device is a PCI-Express device.
3. The method of claim 1 , wherein the device is a host bus adapter coupled to the computing system using a PCI-Express link.
4. The method of claim 1 , wherein the device is a converged network adapter coupled to the computing system using a PCI-Express link.
5. The method of claim 1 , wherein the device is an adapter coupled to the computing system using a PCI-Express link.
6. The method of claim 1 , wherein a transmit scheduler controls an order in which data is read from one or more memory storage locations of the device.
7. The method of claim 1 , wherein when the number of input/output (I/O) requests is greater than the number of available direct memory access (DMA) channels, then using a dedicated DMA channel for each I/O request for transferring any data from the memory of the computing system.
8. The method of claim 1 , wherein the IOCB includes an address of the memory at the computing system where the data is stored prior to the transfer and a length indicating an amount of data stored at the memory of the computing system.
9. A system, comprising:
a computing system having a memory and a processor; and
a device interfacing with the computing system for receiving data from the memory of the computing system to a memory device of the device;
wherein the device is configured to receive an input/output control block (IOCB) from the computing system for transferring the data from the memory of the computing system to the device; allocates a plurality of DMA channels to the IOCB for transferring the data from the memory of the computing system, when a number of pending input/output (I/O) requests when the IOCB is received is less than a number of available direct memory access (DMA) channels to receive the data from the memory of the computing system; receives portions of the data from the memory of the computing system and saves the portions of data at one or more memory storage locations at the device; tracks an order in which the portions of data are received for the IOCB compared to any other pending request; and transmits the data to another device via a link.
10. The system of claim 9 , wherein the device is a PCI-Express device.
11. The system of claim 9 , wherein the device is a host bus adapter coupled to the computing system using a PCI-Express link.
12. The system of claim 9 , wherein the device is a converged network adapter coupled to the computing system using a PCI-Express link.
13. The system of claim 9 , wherein the device is an adapter coupled to the computing system using a PCI-Express link.
14. The system of claim 9 , wherein a transmit scheduler controls an order in which data is read from one or more memory storage locations of the device.
15. The system of claim 9 , wherein when the number of input/output (I/O) requests is greater than the number of available direct memory access (DMA) channels, then using a dedicated DMA channel for each I/O request for transferring data from the memory of the computing system.
16. The system of claim 9 , wherein the IOCB includes an address of the memory at the computing system where the data is stored prior to the transfer and a length indicating an amount of data stored at the memory of the computing system.
17. A device, comprising:
an interface for communicating with a computing system having a memory and a processor;
a plurality of direct memory access (DMA) channels managed by a DMA module for transferring data from the memory of the computing system; and
a memory device for receiving data from the memory of the computing system;
wherein the device is configured to receive an input/output control block (IOCB) from the computing system for transferring the data from the memory of the computing system to the device; allocates more than one DMA channel to the IOCB for transferring the data from the memory of the computing system, when a number of pending input/output (I/O) requests when the IOCB is received is less than a number of available DMA channels to receive the data from the memory of the computing system; receives portions of the data from the memory of the computing system and saves the portions of data at one or more memory storage locations at the device; tracks an order in which the portions of data for the IOCB are received compared to any other pending request; and transmits the data to another device via a link.
18. The device of claim 17 , wherein the device is a PCI-Express device.
19. The device of claim 17 , wherein the device is a host bus adapter or a converged network adapter coupled to the computing system using a PCI-Express link.
20. The device of claim 17 , wherein when the number of input/output (I/O) requests is greater than the number of available direct memory access (DMA) channels, then using a dedicated DMA channel for each I/O request for transferring any data from the memory of the computing system.