Controlled multi-step de-alignment of clocks

1. A method for controlling operation of a system that extends across at least two clock domains and that comprises a plurality of functional units in different clock domains, wherein said plurality of functional units comprises a first functional unit and a second functional unit, said method comprising:

driving said first functional unit in a first clock domain with a first clock-signal,

driving said second functional unit in a second clock domain with a second clock-signal,

receiving said first clock-signal from a first clock-signal source,

providing a phase delay with respect to said first clock-signal from a component within said first functional unit for use within said first functional unit,

providing said second clock-signal by delaying said first clock-signal using a first delay line,

receiving reference information indicative of said phase delay from a component within said first functional unit by interrogating said component, wherein a target time-domain offset between said first and second clock-signals is based on said phase delay, and

dynamically controlling said first delay line to cause said second clock-signal to sustain a temporal offset that causes an offset between said first and second clock-signals to take a step toward said target time-domain offset, and wherein said step has a first step-size that is independent of a difference between said target time-domain offset and said offset between said first and second clock signals.

2. The method of claim 1 , wherein said first step-size has a first value common to all phase discrepancies within a first range of phase-discrepancies, and wherein said first step-size is smaller than any value of phase discrepancy in said first range of phase discrepancies.

3. The method of claim 2 , wherein, within a second range of phase discrepancies, said step has a second step-size that is independent of phase discrepancy within said second range.

4. The method of claim 1 , wherein said first step-size is inadequate to reach said target phase-offset.

5. The method of claim 1 , wherein causing a phase difference between said first clock-signal and said second clock-signal to take a step toward said target phase-offset occurs during a first period from a first set of first periods, wherein each first period from said set of first periods is between a first second-period and a second second-period from a set of second periods, and wherein each second period from said set of second periods is between a first first-period and a second first-period from said set of first periods.

6. The method of claim 5 , wherein during first periods from said set of first periods, said system is quiescent.

7. The method of claim 6 , wherein said first periods consist of memory-refresh intervals.

8. The method of claim 1 , wherein causing a phase difference between said first clock-signal and said second clock-signal to take a step toward said target time-domain offset occurs multiple times, each of which takes place during a first period from a first set of first periods, wherein each of said first periods from said set of first periods is between a first second-period and a second second-periods from a set of second periods, and wherein each second period from said set of second periods is between a first first-period and a second first-period from said set of first periods.

9. The method of claim 1 , wherein the component within said first functional unit comprises a first delay line having delay-line outputs, and receiving reference information indicative of said phase delay comprises receiving information indicative of a phase difference that is caused by said first delay line, and wherein causing an offset between said first and second clock-signals to take a step toward said target time-domain offset comprises changing a delay-line setting from which said second clock-signal is obtained based on inspection of characteristics of a second delay line.

10. The method of claim 9 , wherein causing an offset between said first and second clock-signals to take a step toward said target time-domain offset comprises causing said delay-line setting to be changed upon detection of a window of opportunity during which said second clock-signal is in a stable state.

11. The method of claim 1 , wherein causing an offset between said first and second clock-signals to take a step toward said target time-domain offset comprises providing a first signal that identifies a range of phase offsets to be applied to said first clock signal and providing a second signal that selects a phase offset from said range of phase offsets.

12. The method of claim 1 , wherein said first step-size is selected to avoid causing a glitch in said second clock-signal.

13. The method of claim 1 , wherein said first step-size is selected to avoid causing cycle compression in said second clock-signal to an extent that reduces margin by more than a specified value.

14. An apparatus for data processing, said apparatus comprising:

a first functional unit in a first clock domain driven by a first clock-signal,

a second functional unit in a second clock domain driven by a second clock-signal,

a first clock-signal source configured to provide said first clock-signal,

a component within said first functional unit that provides a phase delay with respect to said first clock-signal for use within said first functional unit,

a first delay line configured to provide said second clock-signal by delaying said first clock-signal, and

a clock-retardation unit configured to interrogate said component within said first functional unit to receive reference information indicative of said phase delay, wherein a target time-domain offset between said first and second clock-signals is based on said phase delay,

wherein said clock-retardation unit is further configured to dynamically control said first delay line to cause said second clock-signal to sustain a temporal offset that causes an offset between said first and second clock-signals to take a step toward said target time-domain offset, and wherein said step has a first step-size that is independent of a difference between said target time-domain offset and said offset between said first and second clock signals.

15. The apparatus of claim 14 , wherein said temporal offset has a step-size, and wherein said step-size is less than a magnitude of a difference between said target time-domain offset and said offset between said first and second clock signals.

16. The apparatus of claim 14 , wherein said clock-retardation unit is configured to control said first delay line to cause said second clock-signal to sustain said temporal offset during a first period from a first set of first periods, wherein each first period from said set of first periods is between a first second-period and a second second-period from a set of second periods, and wherein each second period from said set of second periods is between a first first-period and a second first-period from said set of first periods.

17. The apparatus of claim 16 , wherein during first periods from said set of first periods, said system is quiescent.

18. The apparatus of claim 17 , wherein said first periods consist of memory-refresh intervals.

19. The apparatus of claim 14 , wherein said clock retardation unit is configured to control said first delay line to cause said second clock-signal to sustain said temporal offset multiple times, each of which takes place during a first period from a first set of first periods, wherein each of said first periods from said set of first periods is between a first second-period and a second second-periods from a set of second periods, and wherein each second period from said set of second periods is between a first first-period and a second first-period from said set of first periods.

20. The apparatus of claim 14 , further comprising a second delay line, wherein said clock-retardation unit is configured to control said first delay line based at least in part on information concerning operation of said second delay line.

21. The apparatus of claim 20 , wherein said clock-retardation unit is configured to control said first delay line to cause said second clock-signal to sustain a temporal offset that causes an offset between said first and second clock-signals to step toward a target time-domain offset between said first and second clock-signals by changing a delay-line setting of said second delay-line upon detection of a window of opportunity during which said second clock-signal is in a stable state.

22. The apparatus of claim 20 , wherein said clock-retardation unit is configured to control said first delay line to cause said second clock-signal to sustain a temporal offset that causes an offset between said first and second clock-signals to step toward a target time-domain offset between said first and second clock-signals by providing a first signal and a second signal to said second delay line, wherein said first signal identifies a range of offsets, and wherein said second signal selects an offset within said range of offsets.

23. The apparatus of claim 14 , wherein said first delay line is connected to said clock-retardation unit, wherein said clock-retardation unit is configured to send first and second signals to said first delay line, wherein said first signal indicates a delay-line setting to be applied to said first delay line, and wherein said delay-line setting is applied to said first delay line at least in part based on said second signal.

24. The apparatus of claim 14 , wherein said clock-retardation unit is configured to cause said second clock-signal to sustain a temporal offset that has an extent that is selected to avoid causing a glitch in said second clock-signal.

25. The apparatus of claim 14 , wherein said clock-retardation unit is configured to cause said second clock-signal to sustain a temporal offset that has an extent that is selected to avoid causing cycle compression in said second clock-signal to an extent that reduces margin by more than a specified value.