Method and system for managing traffic in fibre channel systems
View Patent ↗Method and system for routing fiber channel frames using a fiber channel switch element is provided. The method includes, inserting a time stamp value in a fiber channel frame that is received at a receive segment of the fibre channel switch element; determining if a timeout occurs after a frame arrives at a receive buffer; and processing the frame if the timeout occurred. The method also includes, determining if a delta time value, which provides an accumulated wait time for a frame, is present in frame data; subtracting the delta time stamp value from a global time stamp value and using the resulting time stamp value to determine frame timeout status in the fiber channel switch element. A timeout checker circuit declares a timeout after comparing a time stamp value that is inserted in a fiber channel frame with a programmed time out value and a global counter value.
1. A time out checker circuit for determining whether a frame timeout has occurred, the circuit comprising:
first logic for receiving at inputs a timeout value and a frame time stamp value, summing the inputs, and generating as an output a frame timeout value, which is equal to the sum of the input;
second logic for receiving as inputs the frame time stamp value and a global real-time counter value, comparing, the inputs, and, if the frame time stamp value is greater than the global real-time counter value, generating as an output a rollover value, which indicates that the global real-time counter value has rolled over from its maximum value to zero; and
third logic for receiving as inputs the global real-time counter value and the frame timeout value, comparing the inputs, and, if the global real-time counter value is greater than or equal to the frame timeout value, generating as an output a frame timeout signal indicating that a frame has timed out.
2. The time out checker circuit or claim 1 , wherein the timeout value is programmed.
3. The time out checker circuit of claim 1 , wherein the frame time stamp value is based on the global real-time counter value.
4. The time out checker circuit of claim 1 , wherein the frame time stamp value is always less than or equal to the global real-time counter value, except when the global real-time counter value has rolled over from its maximum value to zero.
5. The time out checker circuit of claim 1 , further comprising a module for holding a rollover state and providing the rollover state to the third logic.
6. A method of determining whether a frame timeout has occurred using a time out checker circuit, the method comprising:
first logic of the time out checker circuit receiving as inputs a timeout value and a frame time stump value, summing the inputs, and generating as an output a frame timeout value, which is equal to the sum of the inputs;
second logic of the time out checker circuit receiving as inputs the frame time stamp value and a global real-time counter value, comparing the inputs, and, if the frame time stamp value is greater than the global real-time counter value, generating as an output a rollover value, which indicates that the global real-time counter value has rolled over from its maximum value to zero; and
third logic o the time out checker circuit receiving as inputs the global real-time counter value and the frame timeout value, comparing the inputs, and, if the global real-time counter value is greater than or equal to the frame timeout value, generating as an output a frame timeout signal indicating that a frame has timeout.
7. The method of claim 6 , further comprising programming the timeout value.
8. The method of claim 6 , wherein the frame time stamp value is based on the global real-time counter value.
9. The method of claim 6 wherein the frame time stamp value is always less than or equal to the global real-time counter value, except when the global real-time counter value has rolled over from its maximum value to zero.
10. The method of claim 6 , further comprising a module for holding a rollover state and providing the rollover state to the third logic.
11. The method of claim 10 , wherein if the timeout value and the frame time stamp value are both values having x bits, the sum of the timeout value and the frame time stamp value has x+1 bits, and another bit is concatenated with the global real-time counter value so that it also has x+1 bits.
12. The method of claim 11 , wherein the rollover state is used as the most significant bit in the concatenated global real-time counter value.