IP Library Granted Patent US 6,961,784
Granted Patent B1
US 6,961,784 · App. 10/417,523 · Granted Nov 1, 2005

Method and system for processing non-data frames in host bus adapters

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Quick Facts
Patent No.
US 6,961,784
App. No.
10/417,523
Granted
Nov 1, 2005
Kind
B1
Abstract

A method and system processing non-data frames in a host bus adapter with a main processor and a first processor coupled to a host system and fibre channel is provided. The method includes, examining non-data frames; storing non-data frame information; notifying the first processor of non-data frames; and processing non-data frames without generating an interrupt for the main processor. The host bust adapter includes a fibre channel module (“FPM”) with a state machine, wherein the fibre channel module receives and examines the non-data frames and stores non-data frame information in a FIFO. The FPM notifies the first processor that the non-data frames have been received.

Claims (23)

1. A method for processing non-data frames by a host bus adapter with a main processor and a first processor, wherein the host bus adapter is coupled to a host system having its own processor and to a fibre channel network, comprising:

examining non-data frames, wherein a state machine in a fibre channel protocol module examines the non-data frames received from the fibre channel network;

extracting frame header information from the on-data frames;

storing non-data frame header information in a receive path of the host bus adapter, wherein a memory located in the fibre channel protocol module stores non-data frame information;

notifying the first processor of non-data frames, wherein a signal from the state machine of the fibre channel protocol module indicates to the first processor that a non-data frame has been received; and

processing non-data frames without generating an interrupt for the main processor of the host bus adapter, wherein the first processor of the host bus adapter processes the non-data frames instead of the main processor of the host bus adapter.

2. The method of claim 1 , wherein the non-data frames are stored in a FIFO based memory in the fibre channel protocol module.

3. The method of claim 1 , further comprising:

uploading the non-data frames for processing, wherein the first processor uploads the non-data frame for processing.

4. The method of claim 1 , wherein the main processor is a RISC processor.

5. The method of claim 1 , wherein the non-data frames may be non-data SCSI frames, including a good status and/or transfer ready frame.

6. A system for processing non-data frames, comprising:

a host bus adapter with a main processor coupled to a host system having its own processor;

a first processor that controls receive operations; and

a fibre channel module with a state machine, wherein the fibre channel module receives non-data frames and the state machine examines the non-data frames, extracts frame header information of the non-data frames and stores non-data frame information in a FIFO in a receive path and notifies the first processor that the non-data frames have been received, wherein the first processor instead of the main processor uploads and processes the non-data frames without sending an interrupt to the main processor.

7. The system of claim 6 , wherein the non-data frames may be non-data SCSI frames, including a good status and/or transfer ready frame.

8. The system of claim 6 , wherein the main processor of the host bus adapter is a RISC processor.

9. A host bus adapter for processing non-data frames operationally coupled to a host system having its own processor, comprising:

a main processor;

a first processor that controls receive operations; and

a fibre channel protocol module with a state machine, wherein the fibre channel protocol module receives non-data frames and the state machine examines the non-data frames, extracts header information of the non-data frames and stores non-data frame information in a FIFO in a receive path and notifies the first processor that the non-data frames have been received, wherein the first processor instead of the main processor uploads and processes the non-data frames without sending an interrupt to the main processor.

10. The host bus adapter of claim 9 , wherein the non-data frames may be non-data SCSI frames, including a good status and/or transfer ready frame.

11. The host bus adapter of claim 9 , wherein the main processor of the host bus adapter is a RISC processor.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CHANGE OF NAME Recorded Oct 8, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047205/0953 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
MERGER Recorded Oct 18, 2017
From: QLOGIC CORPORATION
To: CAVIUM, INC.
Reel/Frame 044812/0504 →
SECURITY AGREEMENT Recorded Mar 1, 2017
From: QLOGIC CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 041854/0119 →