IP Library Granted Patent US 7,392,437
Granted Patent B2
US 7,392,437 · App. 11/039,189 · Granted Jun 24, 2008

Method and system for testing host bus adapters

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Quick Facts
Patent No.
US 7,392,437
App. No.
11/039,189
Granted
Jun 24, 2008
Kind
B2
Abstract

A system and method to test a host bus adapter's (“HBAs”) ability to handle stream of invalid characters is provided. A data presenter module presents data to a HBA without being aware of a data format. A data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations. A bit offset change module changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters.

Claims (21)

1. A system for testing a host bus adapter's (“HBA's”) ability to handle stream of invalid characters, comprising:

a computing system coupled to the HBA, where the computing system executes codes for: (a) a data presenter module that presents data to a HBA without being aware of a data format; (b) a data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations; and (c) a bit offset change module that changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters.

2. The system of claim 1 , wherein the data presenter module sends 20-bit blocks of data.

3. The system of claim 1 , wherein the data producer module creates 8-bit data, converts the 8-bit data into 10-bit data, before sending the 10-bit data to a circular buffer.

4. The system of claim 3 , wherein the circular buffer is used for staging random data streams, before sending the data to the HBA.

5. The system of claim 1 , wherein the data presenter module, the data producer module and the bit offset module operate in parallel.

6. A method for testing a host bus adapter's (“HBA's”) ability to handle stream of invalid characters, comprising:

selecting random data, wherein a data producer module selects random data and is aware of a data format, and schedules special characters in the random data so that the HBA can perform alignment operations;

converting the random data to a format that is acceptable to a receive channel in the HBA; and

setting a bit off-set that results in loss of alignment in the HBA and causes the HBA to decode invalid characters, wherein a bit-offset module sets the bit offset.

7. The method of claim 6 , wherein a data presenter module sends 20-bit blocks of data to the HBA.

8. The method of claim 7 , wherein the data presenter module is unaware of the data format in which data is presented to the HBA.

9. The method of claim 6 , wherein the data producer module creates 8-bit data, converts the 8-bit data into 10-bit data, before sending the 10-bit data to a circular buffer.

10. The method of claim 9 , wherein the circular buffer is used for staging random data streams, before sending the data streams to the HBA.

11. The method of claim 6 , wherein a data presenter module, the data producer module and the bit offset module operate in parallel.

12. A testing module for testing a host bus adapter's (“HBA's”) ability to handle stream of invalid characters, comprising:

a computing system coupled to the HBA via a serial interface, where the computing system executes code for: (a) a data presenter module that presents data to a HBA without being aware of a data format; (b) a data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations; and (c) a bit offset change module that changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters.

13. The testing module of claim 12 , wherein the data presenter module sends 20-bit blocks of data.

14. The testing module of claim 12 , wherein the data producer module creates 8-bit data, converts the 8-bit data into 10-bit data, before sending the 10-bit data to a circular buffer.

15. The testing module of claim 14 , wherein the circular buffer is used for staging random data streams, before sending the data to the HBA.

16. The testing module of claim 12 , wherein the data presenter module, the data producer module and the bit offset module operate in parallel.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CHANGE OF NAME Recorded Oct 8, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047205/0953 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
MERGER Recorded Oct 18, 2017
From: QLOGIC CORPORATION
To: CAVIUM, INC.
Reel/Frame 044812/0504 →
SECURITY AGREEMENT Recorded Mar 1, 2017
From: QLOGIC CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 041854/0119 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2005
From: BOWLBY, GAVIN J.; WOODRAL, DAVID E.
To: QLOGIC CORPORATION
Reel/Frame 016202/0046 →