Parser engine programming tool for programmable network devices
View Patent ↗A parser engine programming tool configured to receive an input file representing a directly connected cyclical graph or tree of decision points for parsing a range of incoming packet headers, automatically generate all possible paths within the graph and thereby the associated possible headers, and convert the determined paths/headers into a proper format for programming memory of a parser engine to parse the determined headers (represented by the paths).
1. A processing network comprising:
a processing circuit having a programmable parser including one or more parsing engines that parse data packets received by the processing circuit; and
a parser compiler stored on a non-transitory computer-readable memory and communicatively coupled with each of the parsing engines, wherein the parser compiler is configured to generate values based on a parser configuration file that when programmed into a memory associated with each of the parsing engines enables the parsing engines to identify each of a set of different combinations of packet headers represented by the parser configuration file, wherein the memory associated with each of the parsing engines comprises ternary content-addressable memory paired with static random-access memory, and further wherein the parsing engines identify the combination of packet headers of one of the data packets based on a first portion of the values stored in the ternary content-addressable memory that indicate the combination of packet header of the one of the data packets and determine what actions to perform with the one of the data packets based on a second portion of the values stored in the static random-access memory paired with the ternary content-addressable memory that indicate the actions to perform with the one of the data packets.
2. The network of claim 1 , wherein the parsing engines parse the data packets by identifying if the combination of headers of each of the data packets is one of the set of different combinations of packet headers.
3. The network of claim 2 , wherein the parser configuration file includes a directly connected cyclical graph having a plurality of paths, wherein a structure of the directly connected cyclical graph corresponds to the set of different combinations of packet headers.
4. The network of claim 3 , wherein the parser compiler generates the values based on the paths of the parser configuration file, and further wherein each of the paths corresponds to a separate combination of packet headers of the set of different combinations of packet headers.
5. The network of claim 4 , wherein the parser compiler determines all of the paths of the directly connected cyclical graph, wherein each of the paths either end and start at the same node within the graph or end at a terminating node within the graph that has no outgoing branches.
6. The network of claim 5 , wherein each type of header of the combinations of packet headers has a layer type and the ternary content-addressable memory comprises a plurality of entries, and further wherein the parser compiler stores the first portion of the values within the ternary content-addressable memory such that headers having different layer types do not occupy the same entry.
7. The network of claim 6 , wherein the parser compiler automatically remove duplicate entries of the entries of the ternary content-addressable memory.
8. The network of claim 7 , wherein different types of the headers of the combinations are able to have the same layer type.
9. A parser compiler stored on a non-transitory computer-readable memory and configured to:
input a parser configuration file; and
generate values based on the parser configuration file that when programmed into a memory associated with each of a plurality of parsing engines enables the parsing engines to identify each of a set of different combinations of packet headers represented by the parser configuration file, wherein the parsing engines are a part of a programmable parser of a processing circuit that parses data packets received by the processing circuit, wherein the memory associated with each of the parsing engines comprises ternary content-addressable memory paired with static random-access memory, and further wherein the parsing engines identify the combination of packet headers of one of the data packets based on a first portion of the values stored in the ternary content-addressable memory that indicate the combination of packet header of the one of the data packets and determine what actions to perform with the one of the data packets based on a second portion of the values stored in the static random-access memory paired with the ternary content-addressable memory that indicate the actions to perform with the one of the data packets.
10. The parser compiler of claim 9 , wherein the parsing engines parse the data packets by identifying if the combination of headers of each of the data packets is one of the set of different combinations of packet headers.
11. The parser compiler of claim 10 , wherein the parser configuration file includes a directly connected cyclical graph having a plurality of paths, wherein a structure of the directly connected cyclical graph corresponds to the set of different combinations of packet headers.
12. The parser compiler of claim 11 , wherein the parser compiler generates the values based on the paths of the parser configuration file, and further wherein each of the paths corresponds to a separate combination of packet headers of the set of different combinations of packet headers.
13. The parser compiler of claim 12 , wherein the parser compiler determines all of the paths of the directly connected cyclical graph, wherein each of the paths either end and start at the same node within the graph or end at a terminating node within the graph that has no outgoing branches.
14. The parser compiler of claim 13 , wherein each type of header of the combinations of packet headers has a layer type and the ternary content-addressable memory comprises a plurality of entries, and further wherein the parser compiler stores the first portion of the values within the ternary content-addressable memory such that headers having different layer types do not occupy the same entry.
15. The parser compiler of claim 14 , wherein the parser compiler automatically remove duplicate entries of the entries of the ternary content-addressable memory.
16. The parser compiler of claim 15 , wherein different types of the headers of the combinations are able to have the same layer type.
17. A method of operating a parser compiler, the method comprising:
inputting a parser configuration file with a parsing device storing the parser compiler; and
generating values with the parser compiler based on the parser configuration file, wherein the values, when programmed into a memory associated with each of a plurality of parsing engines, enable the parsing engines to identify each of a set of different combinations of packet headers represented by the parser configuration file, wherein the parsing engines are a part of a programmable parser of a processing circuit that parses data packets received by the processing circuit, wherein the memory associated with each of the parsing engines comprises ternary content-addressable memory paired with static random-access memory, and further wherein the parsing engines identify the combination of packet headers of one of the data packets based on a first portion of the values stored in the ternary content-addressable memory that indicate the combination of packet header of the one of the data packets and determine what actions to perform with the one of the data packets based on a second portion of the values stored in the static random-access memory paired with the ternary content-addressable memory that indicate the actions to perform with the one of the data packets.
18. The method of claim 17 , wherein the parsing engines parse the data packets by identifying if the combination of headers of each of the data packets is one of the set of different combinations of packet headers.
19. The method of claim 18 , wherein the parser configuration file includes a directly connected cyclical graph having a plurality of paths, wherein a structure of the directly connected cyclical graph corresponds to the set of different combinations of packet headers.
20. The method of claim 19 , wherein the generating of the values is based on the paths of the parser configuration file, and further wherein each of the paths corresponds to a separate combination of packet headers of the set of different combinations of packet headers.
21. The method of claim 20 , further comprising determining all of the paths of the directly connected cyclical graph with the parser compiler, wherein each of the paths either end and start at the same node within the graph or end at a terminating node within the graph that has no outgoing branches.
22. The method of claim 21 , wherein each type of header of the combinations of packet headers has a layer type and the ternary content-addressable memory comprises a plurality of entries, further comprising storing the first portion of the values within the ternary content-addressable memory with the parser compiler such that headers having different layer types do not occupy the same entry.
23. The method of claim 22 , further comprising automatically removing duplicate entries of the entries of the ternary content-addressable memory with the parser compiler.
24. The method of claim 23 , wherein different types of the headers of the combinations are able to have the same layer type.