Patent Assignment
Reel/Frame 047577/0653
Change of Name
Recorded: 2018-09-27
Pages: 10
Assignor
CAVIUM, INC.
Executed: 2018-09-24
Assignee
CAVIUM, LLC
5488 MARVELL LN, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(85)
System for and Method of Combining Cmos Inverters of Multiple Drive Strengths to Create Tune-Able Clock Inverters of Variable Drive Strengths in Hybrid Tree-Mesh Clock Distribution Networks
System for and Method of Placing Clock Stations Using Variable Drive-Strength Clock Drivers Built Out of a Smaller Subset of Base Cells for Hybrid Tree-Mesh Clock Distribution Networks
System for and Method of Tuning Clock Networks Constructed Using Variable Drive-Strength Clock Inverters with Variable Drive-Strength Clock Drivers Built Out of a Smaller Subset of Base Cells
Matrix of on-Chip Routers Interconnecting a Plurality of Processing Engines and a Method of Routing Using Thereof
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Method and Apparatus for Parallel and Conditional Data Manipulation in a Software-Defined Network Processing Engine
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Method and Apparatus for Analytics in a Network Switch
Method and Apparatus for Table Aging in a Network Switch
Hierarchical Statistically Multiplexed Counters and a Method Therof
Method of Modifying Packets to a Generic Format for Enabling Programmable Modifications and an Apparatus Thereof
Method of Representing a Generic Format Header Using Continuous Bytes and an Apparatus Thereof
Method of Using a Unique Packet Identifier to Identify Structure of a Packet and an Apparatus Thereof
Method of Using Generic Modification Instructions to Enable Flexible Modifications of Packets and an Apparatus Thereof
Method of Using Bit Vectors to Allow Expansion and Collapse of Header Layers Within Packets for Enabling Flexible Modifications and an Apparatus Thereof
Method of Splitting a Packet into Individual Layers for Modification and Intelligently Stitching Layers Back Together After Modification and an Apparatus Thereof
Method of Extracting Data from Packets and an Apparatus Thereof
Method of Forming a Hash Input from Packet Contents and an Apparatus Thereof
Method of Handling Large Protocol Layers for Configurable Extraction of Layer Information and an Apparatus Thereof
Method of Reducing Latency in a Flexible Parser and an Apparatus Thereof
Method of Dynamically Renumbering Ports and an Apparatus Thereof
Method of Identifying Internal Destinations of Network Packets and an Apparatus Thereof
Baseboard Interconnection Device, System and Method
Hierarchical Hardware Linked List Approach for Multicast Replication Engine in a Network Asic
Fast Hardware Switchover in a Control Path in a Network Asic
Session Based Packet Mirroring in a Network Asic
Multicast Replication Engine of a Network Asic and Methods Thereof
Apparatus and a Method of Detecting Errors on Registers
Two Modes of a Configuration Interface of a Network Asic
Smart Holding Registers to Enable Multiple Register Accesses
Multiple-Interrupt Propagation Scheme in a Network Asic
Hybrid Wildcard Match Table
Management of an Over-Subscribed Shared Buffer
Testbench Builder, System, Device and Method
Testbench Builder, System, Device and Method Including a Dispatcher
Testbench Builder, System, Device and Method Including a Generic Monitor and Transporter
Testbench Builder, System, Device and Method Having Agent Loopback Functionality
Packet Processor Forwarding Database Cache
Phantom Queue Link Level Load Balancing System, Method and Device
Testbench Builder, System, Device and Method with Phase Synchronization
Co-Verification - of Hardware and Software, a Unified Approach in Verification
Patent:
9,372,772 →
Application:
14/671,993 →
Software Assisted Hardware Configuration for Software Defined Network System-On-Chip
Packet Tracking in a Verification Environment
Testbench Builder, System, Device and Method Including Latency Detection
Packet Memory System, Method and Device for Preventing Underrun
Packet Processing System, Method and Device to Optimize Packet Buffer Space
Packet Processing System, Method and Device Having Reduced Static Power Consumption
Packet Processing System, Method and Device Utilizing a Port Client Chain
Packet Processing System, Method and Device Utilizing Memory Sharing
Control Path Subsystem, Method and Device Utilizing Memory Sharing
Datapath Subsystem, Method and Device Utilizing Memory Sharing
Parser Engine Programming Tool for Programmable Network Devices
Code Processor to Build Orthogonal Execution Blocks for Programmable Network Devices
Algorithm to Achieve Optimal Layout of Decision Logic Elements for Programmable Network Devices
Algorithm to Derive Logic Expression to Select Execution Blocks for Programmable Network Devices
Algorithm to Achieve Optimal Layout of Instruction Tables for Programmable Network Devices
Code Generator for Programmable Network Devices
Compiler Architecture for Programmable Application Specific Integrated Circuit Based Network Devices
Barrel Compactor System, Method and Device
Barrel Compactor System, Method and Device Having Cell Combination Logic
Policer Architecture
Hybrid Wildcard Match Table
Protocol Independent Programmable Switch (Pips) Software Defined Data Center Networks
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Hierarchical Statisically Multiplexed Counters and a Method Thereof
Packet Processing System, Method and Device Utilizing a Port Client Chain
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Method of Identifying Internal Destinations of Network Packets and an Apparatus Thereof
Method of Using Bit Vectors to Allow Expasion and Collapse of Header Layers Within Packets for Enabling Flexible Modifications and an Apparatus Thereof
Packet Processing System, Method and Device Utilizing Memory Sharing
Fast Hardware Switchover in a Control Path in a Network Asic
Method of Dynamically Renumbering Ports and an Apparatus Thereof
Session Based Packet Mirroring in a Network Asic
Method and Apparatus for Table Aging in a Network Switch
Hierarchical Hardware Linked List Approach for Multicast Replication Engine in a Network Asic
Protocol Independent Programmable Switch (Pips) for Software Defined Data Center Networks
Compiler Architecture for Programmable Application Specific Integrated Circuit Based Network Devices
Phantom Queue Link Level Load Balancing System, Method and Device
Barrel Compactor System, Method and Device
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Method of Implementing a Network Asic in a Network Device
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Hierarchical Statisically Multiplexed Counters and a Method Thereof
Phantom Queue Link Level Load Balancing System, Method and Device
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Release of Security Interest
Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
Assignment of Assignor's Interest
Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
Assignment of Assignor's Interest
May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →