Smart holding registers to enable multiple register accesses
View Patent ↗A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2 n , where n is the number of bits in the source identifier.
1. A processor comprising:
target registers;
N holding registers, wherein each of the N holding registers is associated with a source and is configured to refrain from pushing any subsets of an update received from the source to one of the target registers until all of the subsets of the update have been received from the source; and
a bus coupling the target registers and the N holding registers, wherein when the bus is accessed by one of the holding registers, the bus includes a source identifier indicating the one of the N holding registers that the access is from.
2. The processor of claim 1 , wherein the N holding registers are located in a slave engine.
3. The processor of claim 1 , wherein the N holding registers simultaneously handle N register transactions.
4. The processor of claim 1 , wherein the target registers are implemented in SRAM.
5. The processor of claim 1 , wherein the target registers are implemented in flip-flops.
6. The processor of claim 1 , wherein the N holding registers are implemented in SRAM.
7. The processor of claim 1 , wherein the N holding registers are implemented in flip-flops.
8. The processor of claim 1 , wherein the source identifier is n-bits wide, and the maximum value of N is 2 n .
9. A processor comprising:
target registers;
N holding registers including a first holding register and a second holding register, wherein the first holding register and the second holding register are simultaneously accessed by a first source and a second source, respectively, without using a semaphore, to receive partial updates therefrom;
a bus coupling the target registers and the N holding registers, wherein the bus transports a transaction; and
a source identifier added to the bus, wherein the source identifier indicates the originator of the transaction on the bus.
10. The processor of claim 9 , wherein the transaction is an access to one of the target registers, wherein the transaction is included in the bus after one of the first holding register and the second holding register has received all of the partial updates.
11. The processor of claim 9 , wherein after the first holding register receives all of the corresponding partial updates, the first holding register pushes all of its contents in the first holding register to one of the target registers.
12. The processor of claim 9 , wherein after the second holding register receives all of the corresponding partial updates, the second holding register pushes all of its contents in the second holding register to one of the target registers.
13. The processor of claim 9 , wherein the originator is one of the first holding register and the second holding register.
14. The processor of claim 9 , wherein the N holding registers are located in a slave engine.
15. The processor of claim 9 , wherein the N holding registers simultaneously handle N register transactions.
16. The processor of claim 9 , wherein the target registers are implemented in SRAM.
17. The processor of claim 9 , wherein the target registers are implemented in flip-flops.
18. The processor of claim 9 , wherein the N holding registers are implemented in SRAM.
19. The processor of claim 9 , wherein the N holding registers are implemented in flip-flops.
20. The processor of claim 9 , wherein the source identifier is n-bits wide, and the maximum value of N is 2 n .
21. A method of implementing a register system, comprising:
accessing at least a portion of N holding registers on a processor of a microchip simultaneously by a plurality of sources, without using a semaphore, such that each of the at least a portion of the N holding registers receives partial updates from a respective source; and
when a last write to an accessed holding register is detected, updating a target register on the processor with contents that are in the accessed holding register, wherein the accessed holding register is one of the at least a portion of N holding registers.
22. The method of claim 21 , wherein updating a target register includes pushing the contents to the target register from the accessed holding register.
23. The method of claim 21 , wherein a source of the plurality of sources is software running on the processor.
24. The method of claim 21 , wherein a source of the plurality of sources is software running on an off chip processor not within the microchip.
25. The method of claim 21 , wherein the target register is implemented in SRAM.
26. The method of claim 21 , wherein the target register is implemented in flip-flops.
27. The method of claim 21 , wherein the N holding registers are implemented in SRAM.
28. The method of claim 21 , wherein the N holding registers are implemented in flip-flops.
29. The method of claim 21 , wherein the N holding registers are located in a slave engine.
30. The method of claim 21 , further comprising, prior to updating a target register:
accessing a bus; and
passing a source identifier through the bus, wherein the source identifier is associated with the accessed holding register.